Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system

Research output: Contribution to journalArticleScientificpeer-review

Researchers

  • K. Sathish Shet
  • A. R. Aswath
  • M. C. Hanumantharaju
  • Xiaozhi Gao

Research units

  • JSS Academy of Technical Education
  • Dayananda Sagar College of Engineering
  • BMS Institute of Technology and Management

Abstract

The most crucial task in real-time processing of steganography algorithms is to reduce the computational delay and increase the throughput of a system. This critical issue is effectively addressed by implementing steganography methods in reconfigurable hardware. In the proposed framework, a new high-speed reconfigurable architectures have been designed for Least Significant Bit (LSB) or multi-bit based image steganography algorithm that suits Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) implementation. The architectures are designed and instantiated to implement the complete steganography system. The proposed system is competent enough to provide larger throughput, since high degrees of pipelining and parallel operations are incorporated at the module level. The evolved architectures are realized in Xilinx Virtex-II Pro XC2V500FG256-6 FPGA device using Register Transfer Level (RTL) compliant Verilog coding and has the capacity to work in real-time at the rate of 183.48 frames/second. Prior to the FPGA/ASIC implementation, the proposed steganography system is simulated in software to validate the concepts intended to implement. The hardware implemented algorithm is tested by varying embedding bit size as well as the resolution of a cover image. As it is clear from the results presented that the projected framework is superior in speed, area and power consumption compared to other researcher’s method.

Details

Original languageEnglish
Pages (from-to)13197-13219
Number of pages23
JournalMultimedia Tools and Applications
Volume76
Issue number11
Early online date12 Jul 2016
Publication statusPublished - Jun 2017
MoE publication typeA1 Journal article-refereed

    Research areas

  • Field Programmable Gate Array, Hiding/extraction, Image steganography, Least Significant Bit, Reconfigurable architectures, Verilog

ID: 6749675