Cycle Count Estimation of VLIW Processors Using Machine Learning

Kari Hepola, Jatan Shrestha, Joonas Multanen, Vivienne Wang, Joni Pajarinen, Pekka Jaaskelainen

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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Abstract

Fast evaluation is important for processor design space exploration in order to increase the probability of encountering the optimal design in the vast space of configurations. Previous work has focused on estimation of dynamic multi-issue processors, which does not consider the effects of a varying instruction-set on the estimation through heuristic compilation. This paper presents a cycle count estimation method for application-specific static multi-issue processors with customizable datapaths via machine learning techniques that can estimate cycle counts for any architecture configuration after the initial profiling of the program. Among the estimated models, the residual neural network model achieves the lowest mean relative error of 4.7% while being orders of magnitude faster than running the recompilation and simulation steps.

Original languageEnglish
Title of host publication2024 IEEE Nordic Circuits and Systems Conference, NORCAS 2024 - Proceedings
EditorsJari Nurmi, Joachim Rodrigues, Luca Pezzarossa, Viktor Aberg, Baktash Behmanesh
PublisherIEEE
ISBN (Electronic)979-8-3315-1766-3
DOIs
Publication statusPublished - 2024
MoE publication typeA4 Conference publication
EventIEEE Nordic Circuits and Systems Conference - Lund, Sweden
Duration: 29 Oct 202430 Oct 2024

Publication series

Name2024 IEEE Nordic Circuits and Systems Conference, NORCAS 2024 - Proceedings

Conference

ConferenceIEEE Nordic Circuits and Systems Conference
Abbreviated titleNORCAS
Country/TerritorySweden
CityLund
Period29/10/202430/10/2024

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