Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review


Research units

  • Tampere University of Technology


In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.


Original languageEnglish
Title of host publicationISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 29 Jul 2016
MoE publication typeA4 Article in a conference publication
EventIEEE International Symposium on Circuits and Systems - Montreal, Canada
Duration: 22 May 201625 May 2016

Publication series

NameIEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4302
ISSN (Electronic)2158-1525


ConferenceIEEE International Symposium on Circuits and Systems
Abbreviated titleISCAS
Internet address

ID: 7189546