Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

Mikko Martelius; Kari Stadius; Jerry Lemberg; Tero Nieminen; Enrico Roverato; Marko Kosunen; Jussi Ryynänen; Lauri Anttila; Mikko Valkama

doi:10.1109/ISCAS.2016.7527339

Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

Mikko Martelius, Kari Stadius, Jerry Lemberg, Tero Nieminen, Enrico Roverato, Marko Kosunen, Jussi Ryynänen, Lauri Anttila, Mikko Valkama

Jussi Ryynänen Group

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

9 Citations (Scopus)

Abstract

In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

Original language	English
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publisher	IEEE
Pages	710-713
Number of pages	4
ISBN (Electronic)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7527339
Publication status	Published - 29 Jul 2016
MoE publication type	A4 Article in a conference publication
Event	IEEE International Symposium on Circuits and Systems - Montreal, Canada Duration: 22 May 2016 → 25 May 2016 http://iscas2016.org/

Publication series

Name	IEEE International Symposium on Circuits and Systems
Publisher	IEEE
ISSN (Print)	0271-4302
ISSN (Electronic)	2158-1525

Conference

Conference	IEEE International Symposium on Circuits and Systems
Abbreviated title	ISCAS
Country	Canada
City	Montreal
Period	22/05/2016 → 25/05/2016
Internet address	http://iscas2016.org/

Access to Document

10.1109/ISCAS.2016.7527339

Link to publication in Scopus

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Martelius, M., Stadius, K., Lemberg, J., Nieminen, T., Roverato, E., Kosunen, M., Ryynänen, J., Anttila, L., & Valkama, M. (2016). Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (pp. 710-713). [7527339] (IEEE International Symposium on Circuits and Systems). IEEE. https://doi.org/10.1109/ISCAS.2016.7527339

Martelius, Mikko ; Stadius, Kari ; Lemberg, Jerry ; Nieminen, Tero ; Roverato, Enrico ; Kosunen, Marko ; Ryynänen, Jussi ; Anttila, Lauri ; Valkama, Mikko. / Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter. ISCAS 2016 - IEEE International Symposium on Circuits and Systems. IEEE, 2016. pp. 710-713 (IEEE International Symposium on Circuits and Systems).

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title = "Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter",

abstract = "In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.",

author = "Mikko Martelius and Kari Stadius and Jerry Lemberg and Tero Nieminen and Enrico Roverato and Marko Kosunen and Jussi Ryyn{\"a}nen and Lauri Anttila and Mikko Valkama",

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Martelius, M, Stadius, K, Lemberg, J, Nieminen, T, Roverato, E, Kosunen, M , Ryynänen, J, Anttila, L & Valkama, M 2016, Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems., 7527339, IEEE International Symposium on Circuits and Systems, IEEE, pp. 710-713, IEEE International Symposium on Circuits and Systems, Montreal, Canada, 22/05/2016. https://doi.org/10.1109/ISCAS.2016.7527339

Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter. / Martelius, Mikko; Stadius, Kari; Lemberg, Jerry; Nieminen, Tero; Roverato, Enrico; Kosunen, Marko ; Ryynänen, Jussi; Anttila, Lauri; Valkama, Mikko.

ISCAS 2016 - IEEE International Symposium on Circuits and Systems. IEEE, 2016. p. 710-713 7527339 (IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

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AU - Martelius, Mikko

AU - Stadius, Kari

AU - Lemberg, Jerry

AU - Nieminen, Tero

AU - Roverato, Enrico

AU - Kosunen, Marko

AU - Ryynänen, Jussi

AU - Anttila, Lauri

AU - Valkama, Mikko

PY - 2016/7/29

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N2 - In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

AB - In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

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