Abstract
This paper describes calibration techniques for downconversion mixers used in integrated direct-conversion receivers. A method of achieving a high even-order intermodulation rejection is presented. Using the method presented, the receiver second-order input intercept point (IIP2) can always be improved by more than 20 dB. The minimum achieved receiver IIP2 after calibration is +38 dBm. A technique to enhance the I/Q-amplitude balance between the quadrature channels is also introduced. A single-balanced adjustable mixer is implemented as a part of a prototype direct-conversion receiver. The receiver chip consists of a low-noise amplifier, mixers and calibration circuitry, a divide-by-two circuit, local oscillator (LO) buffers for LO generation, and active baseband filters. The chip is fabricated using a 0.35-μm SiGe BiCMOS process and is characterized at 900 MHz.
Original language | English |
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Pages (from-to) | 766-769 |
Number of pages | 4 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 37 |
Issue number | 6 |
DOIs | |
Publication status | Published - Jun 2002 |
MoE publication type | A1 Journal article-refereed |
Keywords
- BiCMOS analog integrated circuits
- Calibration
- Dc offset
- Direct conversion
- IIP2
- Mixers
- Radio receivers