An apparatus and a method for encoding a sampled phase signal. The apparatus receives an input from a sub-gate-delay resolution arrangement and has a processing circuitry configured to invert selectively a set of bits in a sampled matrix sampled at a sampling instance based on a first predefined reference node of the sub-gate-delay resolution arrangement in order to provide a unary code. The unary code is then compressed and used in unfolding a mapping based on the compressed unary code using a value of a chosen bit. Then the apparatus is provide an output based on said unfolding. As a result the arrangement provides a possibility to use a sub-gate-delay for several different applications.
|IPC||H03M 7/ 16 A I|
|Publication status||Published - 10 Mar 2021|
|MoE publication type||H1 Granted patent|