An Implementation of Simulated Annealing for Analog Circuit Optimization

V. Starck, M. Valtonen

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    Original languageEnglish
    Title of host publicationThe 5th Biennial Conference on Electronics and Microsystems Technology
    Place of PublicationTallinn
    PublisherTallinn Technical University
    Pages377-380
    Publication statusPublished - 1996
    MoE publication typeA4 Article in a conference publication

    Keywords

    • APLAC
    • CAD
    • global optimization
    • simulated annealing

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