An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

Muneeb Abrar*, Hassan Elahi, Bilal Ali Ahmad, Muhammad Ghayasudin, M. Rizwan Mughal

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review


A unique design for an optimized N-bit multiplier is proposed and implemented which utilizes a modified divide-and-conquer technique. The conventional technique requires four N/2-bit multipliers to perform N-bit multiplication, whereas the proposed design uses only one multiplier module in hardware to perform the functionality of four modules. It uses Dadda algorithm in its multiplier module. It has been implemented using Verilog HDL, and a good accuracy of results was observed in simulations which effectively verify its functionality. Design was also synthesized on various FPGAs including Spartan 3E, Virtex-5 and Virtex-7. Performance summary, after place and route, showed that the proposed approach significantly reduces hardware utilization. Furthermore, the proposed design is almost 75% more efficient in terms of resources utilization and operating frequency as compared to the conventional design.

Original languageEnglish
Article number1348
Number of pages6
JournalSN Applied Sciences
Issue number11
Publication statusPublished - Nov 2019
MoE publication typeA1 Journal article-refereed


  • Multiplier
  • Area efficient
  • Divide and conquer

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