An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

Jonne Poikonen, Mika Laiho, Ari Paasio, Lauri Koskinen, Kari Halonen

    Research output: Contribution to journalArticleScientificpeer-review

    1 Citation (Scopus)
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    Abstract

    A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations, reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A Open image in new window cell parallel analog test array for reference-shift with a maximum block-size of Open image in new window, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 Open image in new windowm CMOS technology.
    Original languageEnglish
    Article number127630
    Pages (from-to)1-11
    JournalEurasip Journal on Advances in Signal Processing
    Volume2009
    DOIs
    Publication statusPublished - 2009
    MoE publication typeA1 Journal article-refereed

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