An ADPLL-based fast start-up technique for sensor radio frequency synthesizers

Liangge Xu*, Saska Lindfors, Jussi Ryynänen

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    1 Citation (Scopus)

    Abstract

    This paper proposes a technique to speed up the start-up process of frequency synthesizers for wireless sensor network (WSN) applications. The proposed technique relies on an all-digital phase-locked loop (ADPLL) architecture to preserve last known settled synthesizer state over an extended power-down period and use it on next power-up. The effect of periodic variations such as a change in die temperature is digitally compensated for by utilizing a simple least mean-square (LMS) adaptation algorithm. Simulations demonstrate that with slow ambient temperature drift, the start-up time of the frequency synthesizer can be dramatically reduced.

    Original languageEnglish
    Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
    Pages388-391
    Number of pages4
    DOIs
    Publication statusPublished - 2008
    MoE publication typeA4 Article in a conference publication
    EventIEEE International Conference on Electronics, Circuits and Systems - St. Julian's, Malta
    Duration: 31 Aug 20083 Sep 2008
    Conference number: 15

    Conference

    ConferenceIEEE International Conference on Electronics, Circuits and Systems
    Abbreviated titleICECS
    CountryMalta
    CitySt. Julian's
    Period31/08/200803/09/2008

    Keywords

    • ADPLL
    • sensor radio
    • start-up

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