All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter

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Abstract

This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.

Details

Original languageEnglish
Title of host publication2015 European Conference on Circuit Theory and Design, ECCTD 2015
Publication statusPublished - 16 Oct 2015
MoE publication typeA4 Article in a conference publication
EventEuropean Conference on Circuit Theory and Design - Trondheim, Norway
Duration: 24 Aug 201526 Aug 2015

Conference

ConferenceEuropean Conference on Circuit Theory and Design
Abbreviated titleECCTD
CountryNorway
CityTrondheim
Period24/08/201526/08/2015

    Research areas

  • CMOS digital integrated circuits, calibration, digital phase locked loops, optimisation, ADPLL phase accumulator speed optimization, CMOS, MIPI M-PHY serial link transmitter, PVT calibration, all-digital phase-locked loop, clock generator, frequency 1.2 GHz to 5.8 GHz, loop type changing criteria, phase digitization process, power saving, size 40 nm, CMOS integrated circuits, Clocks, Delays, Monitoring, Phase locked loops, Pipeline processing, Transmitters

ID: 1956468