All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter

Yury Antonov; Tero Tikka; Kari Stadius; Jussi Ryynänen

doi:10.1109/ECCTD.2015.7300035

All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter

Yury Antonov, Tero Tikka, Kari Stadius, Jussi Ryynänen

Jussi Ryynänen Group

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

1 Citation (Scopus)

56 Downloads (Pure)

Abstract

This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.

Original language	English
Title of host publication	2015 European Conference on Circuit Theory and Design, ECCTD 2015
Publisher	IEEE
ISBN (Electronic)	978-1-4799-9876-0
ISBN (Print)	978-1-4799-9877-7
DOIs	https://doi.org/10.1109/ECCTD.2015.7300035
Publication status	Published - 16 Oct 2015
MoE publication type	A4 Conference publication
Event	European Conference on Circuit Theory and Design - Trondheim, Norway Duration: 24 Aug 2015 → 26 Aug 2015

Conference

Conference	European Conference on Circuit Theory and Design
Abbreviated title	ECCTD
Country/Territory	Norway
City	Trondheim
Period	24/08/2015 → 26/08/2015

Keywords

CMOS digital integrated circuits
calibration
digital phase locked loops
optimisation
ADPLL phase accumulator speed optimization
CMOS
MIPI M-PHY serial link transmitter
PVT calibration
all-digital phase-locked loop
clock generator
frequency 1.2 GHz to 5.8 GHz
loop type changing criteria
phase digitization process
power saving
size 40 nm
CMOS integrated circuits
Clocks
Delays
Monitoring
Phase locked loops
Pipeline processing
Transmitters

Access to Document

10.1109/ECCTD.2015.7300035

Antonov_All-Digital_Phase-Locked_IEEEAccepted author manuscript, 2.5 MB

Cite this

@inproceedings{277a0097e13b4bc3bc2d4ec67be00f40,

title = "All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter",

abstract = "This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.",

keywords = "CMOS digital integrated circuits, calibration, digital phase locked loops, optimisation, ADPLL phase accumulator speed optimization, CMOS, MIPI M-PHY serial link transmitter, PVT calibration, all-digital phase-locked loop, clock generator, frequency 1.2 GHz to 5.8 GHz, loop type changing criteria, phase digitization process, power saving, size 40 nm, CMOS integrated circuits, Clocks, Delays, Monitoring, Phase locked loops, Pipeline processing, Transmitters",

author = "Yury Antonov and Tero Tikka and Kari Stadius and Jussi Ryyn{\"a}nen",

year = "2015",

month = oct,

day = "16",

doi = "10.1109/ECCTD.2015.7300035",

language = "English",

isbn = "978-1-4799-9877-7",

booktitle = "2015 European Conference on Circuit Theory and Design, ECCTD 2015",

publisher = "IEEE",

address = "United States",

note = "European Conference on Circuit Theory and Design, ECCTD ; Conference date: 24-08-2015 Through 26-08-2015",

}

TY - GEN

T1 - All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter

AU - Antonov, Yury

AU - Tikka, Tero

AU - Stadius, Kari

AU - Ryynänen, Jussi

PY - 2015/10/16

Y1 - 2015/10/16

N2 - This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.

AB - This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.

KW - CMOS digital integrated circuits

KW - calibration

KW - digital phase locked loops

KW - optimisation

KW - ADPLL phase accumulator speed optimization

KW - CMOS

KW - MIPI M-PHY serial link transmitter

KW - PVT calibration

KW - all-digital phase-locked loop

KW - clock generator

KW - frequency 1.2 GHz to 5.8 GHz

KW - loop type changing criteria

KW - phase digitization process

KW - power saving

KW - size 40 nm

KW - CMOS integrated circuits

KW - Clocks

KW - Delays

KW - Monitoring

KW - Phase locked loops

KW - Pipeline processing

KW - Transmitters

UR - http://www.scopus.com/inward/record.url?scp=84959513462&partnerID=8YFLogxK

U2 - 10.1109/ECCTD.2015.7300035

DO - 10.1109/ECCTD.2015.7300035

M3 - Conference article in proceedings

SN - 978-1-4799-9877-7

BT - 2015 European Conference on Circuit Theory and Design, ECCTD 2015

PB - IEEE

T2 - European Conference on Circuit Theory and Design

Y2 - 24 August 2015 through 26 August 2015

ER -

All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this