All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter

Yury Antonov, Tero Tikka, Kari Stadius, Jussi Ryynänen

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

1 Citation (Scopus)
31 Downloads (Pure)


This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.

Original languageEnglish
Title of host publication2015 European Conference on Circuit Theory and Design, ECCTD 2015
ISBN (Electronic)978-1-4799-9876-0
ISBN (Print)978-1-4799-9877-7
Publication statusPublished - 16 Oct 2015
MoE publication typeA4 Conference publication
EventEuropean Conference on Circuit Theory and Design - Trondheim, Norway
Duration: 24 Aug 201526 Aug 2015


ConferenceEuropean Conference on Circuit Theory and Design
Abbreviated titleECCTD


  • CMOS digital integrated circuits
  • calibration
  • digital phase locked loops
  • optimisation
  • ADPLL phase accumulator speed optimization
  • CMOS
  • MIPI M-PHY serial link transmitter
  • PVT calibration
  • all-digital phase-locked loop
  • clock generator
  • frequency 1.2 GHz to 5.8 GHz
  • loop type changing criteria
  • phase digitization process
  • power saving
  • size 40 nm
  • CMOS integrated circuits
  • Clocks
  • Delays
  • Monitoring
  • Phase locked loops
  • Pipeline processing
  • Transmitters


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