Achieving Near-Ideal Subthreshold Swing in P-Type WSe₂ Field-Effect Transistors

The pursuit of near-ideal subthreshold swing (SS) ≈ 60 mV dec⁻¹ is a primary driving force to realize the power-efficient field-effect transistors (FETs). This challenge is particularly pronounced in 2D material-based FETs, where the presence of a large interface trap density (D_it) imposes limitations on electrostatic control, consequently escalating power consumption. In this study, the gate controllability of 2D FETs is systematically analyzed by fabricating pre-patterned van der Waals (vdW)-contacted p-FETs, varying the WSe₂ channel thickness from monolayer to ten-layer. As a result, the channel thickness is optimized to achieve efficient gate controllability while minimizing D_it. The findings demonstrate negligible hysteresis and excellent subthreshold swing (SS_min) close to the thermal limit (≈60 mV dec⁻¹), with a corresponding D_it of ≈10¹⁰ cm⁻² eV⁻¹, comparable to D_it values observed in state-of-the-art Si transistors, when utilizing WSe₂ channel thicknesses ≥ five-layer. However, reducing the WSe₂ channel thickness below the trilayer, SS_min (≈91 mV dec⁻¹) deviates from the thermal limit, attributed to a comparatively higher D_it (≈10¹¹ cm⁻² eV⁻¹), despite the still lower than values reported for surface-contacted 2D transistors. Furthermore, all devices exhibit consistent p-type characteristics, featuring a high I_ON/I_OFF ratio, high mobility, and excellent electrical stability confirmed over several months.