A2.4-GHzLow-Power All-Digital Phase-Locked Loop

Liangge Xu; Jussi Ryynänen

A2.4-GHzLow-Power All-Digital Phase-Locked Loop

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

Original language	English
Title of host publication	IEEE Custom Integrated Circuits Conference, San Jose, USA, Sept. 2009
Pages	331-334
Publication status	Published - 2009
MoE publication type	A4 Article in a conference publication

Keywords

ADPLL
DCO
FDC
frequency synthesizer
Low power
variable phase accumulator

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Cite this

@inproceedings{88baeccadda94df68f15417c3756dd4e,

title = "A2.4-GHzLow-Power All-Digital Phase-Locked Loop",

keywords = "ADPLL, DCO, FDC, frequency synthesizer, Low power, variable phase accumulator, ADPLL, DCO, FDC, frequency synthesizer, Low power, variable phase accumulator, ADPLL, DCO, FDC, frequency synthesizer, Low power, variable phase accumulator",

author = "Liangge Xu and Jussi Ryyn{\"a}nen",

year = "2009",

language = "English",

pages = "331--334",

booktitle = "IEEE Custom Integrated Circuits Conference, San Jose, USA, Sept. 2009",

}

TY - GEN

T1 - A2.4-GHzLow-Power All-Digital Phase-Locked Loop

AU - Xu, Liangge

AU - Ryynänen, Jussi

PY - 2009

Y1 - 2009

KW - ADPLL

KW - DCO

KW - FDC

KW - frequency synthesizer

KW - Low power

KW - variable phase accumulator

KW - ADPLL

KW - DCO

KW - FDC

KW - frequency synthesizer

KW - Low power

KW - variable phase accumulator

KW - ADPLL

KW - DCO

KW - FDC

KW - frequency synthesizer

KW - Low power

KW - variable phase accumulator

M3 - Conference contribution

SP - 331

EP - 334

BT - IEEE Custom Integrated Circuits Conference, San Jose, USA, Sept. 2009

ER -