A wideband blocker-resilient direct delta sigma receiver with selective input-impedance matching

Faizan Ul Haq*, Mikko Englund, Kim B. Östman, Kari Stadius, Marko Kosunen, Kimmo Koli, Jussi Ryynänen

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

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This paper presents a wideband blocker-tolerant direct DR receiver (DDSR). Blockers are attenuated through selective input impedance matching and reduced gain design. The selective input impedance profile provides a low impedance at blocker frequencies enabling blocker attenuation, while the in-band impedance is boosted to matched condition through an up-converted positive feedback from the DDSR output. In addition, with the help of reduced gain design, near band blocker gain is minimized, further improving the blocker resilience. The receiver is designed for configurable operation from 0.7-2.7 GHz and a baseband bandwidth of 10 MHz. Simulated in a 28 nm technology, the DDSR demonstrates a maximum noise figure of 6.2 dB, and achieves a peak SNDR of 53 dB with an out-of-band 1 dB input compression point of - 11 dBm at a 100 MHz offset.

Original languageEnglish
Pages (from-to)195–207
Number of pages13
JournalAnalog Integrated Circuits and Signal Processing
Issue number1
Publication statusPublished - 1 Apr 2020
MoE publication typeA1 Journal article-refereed


  • Blocker tolerance
  • Selective impedance matching
  • Tunable bandpass filtering
  • Low noise amplifier
  • Direct delta sigma receiver
  • ADC


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