A temperature and process compensation circuit for resistive-based in-memory computing arrays

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Abstract

In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.

Original languageEnglish
Title of host publicationISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings
PublisherIEEE
ISBN (Electronic)978-1-6654-5109-3
ISBN (Print)978-1-6654-5110-9
DOIs
Publication statusPublished - 2023
MoE publication typeA4 Conference publication
EventIEEE International Symposium on Circuits and Systems - Monterey, United States
Duration: 21 May 202325 May 2023
Conference number: 56

Publication series

NameIEEE International Symposium on Circuits and Systems proceedings
Volume2023-May
ISSN (Print)0271-4310
ISSN (Electronic)2158-1525

Conference

ConferenceIEEE International Symposium on Circuits and Systems
Abbreviated titleISCAS
Country/TerritoryUnited States
CityMonterey
Period21/05/202325/05/2023

Keywords

  • In-memory computing
  • process compensation
  • Resistive random access memory
  • Thermal compensation
  • ultra-low power
  • variable temperature coefficient

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