A temperature and process compensation circuit for resistive-based in-memory computing arrays

Dipesh C. Monga; Omar Numan; Martin Andraud; Kari Halonen

doi:10.1109/ISCAS46773.2023.10181619

A temperature and process compensation circuit for resistive-based in-memory computing arrays

Dipesh C. Monga, Omar Numan, Martin Andraud, Kari Halonen

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

4 Citations (Scopus)

59 Downloads (Pure)

Abstract

In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.

Original language	English
Title of host publication	ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings
Publisher	IEEE
ISBN (Electronic)	978-1-6654-5109-3
ISBN (Print)	978-1-6654-5110-9
DOIs	https://doi.org/10.1109/ISCAS46773.2023.10181619
Publication status	Published - 2023
MoE publication type	A4 Conference publication
Event	IEEE International Symposium on Circuits and Systems - Monterey, United States Duration: 21 May 2023 → 25 May 2023 Conference number: 56

Publication series

Name	IEEE International Symposium on Circuits and Systems proceedings
Volume	2023-May
ISSN (Print)	0271-4310
ISSN (Electronic)	2158-1525

Conference

Conference	IEEE International Symposium on Circuits and Systems
Abbreviated title	ISCAS
Country/Territory	United States
City	Monterey
Period	21/05/2023 → 25/05/2023

Keywords

In-memory computing
process compensation
Resistive random access memory
Thermal compensation
ultra-low power
variable temperature coefficient

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISCAS46773.2023.10181619

Monga_Temperature_and_process_compensation_RSENSEAccepted author manuscript, 2.87 MB

Cite this

Monga, D. C., Numan, O., Andraud, M., & Halonen, K. (2023). A temperature and process compensation circuit for resistive-based in-memory computing arrays. In ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings (IEEE International Symposium on Circuits and Systems proceedings; Vol. 2023-May). IEEE. https://doi.org/10.1109/ISCAS46773.2023.10181619

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title = "A temperature and process compensation circuit for resistive-based in-memory computing arrays",

abstract = "In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.",

keywords = "In-memory computing, process compensation, Resistive random access memory, Thermal compensation, ultra-low power, variable temperature coefficient",

author = "Monga, {Dipesh C.} and Omar Numan and Martin Andraud and Kari Halonen",

note = "Funding Information: ACKNOWLEDGMENTS This work is supported by Academy of Finland projects EHIR (grant 13334487) and WHISTLE (grant 332218) Publisher Copyright: {\textcopyright} 2023 IEEE.; IEEE International Symposium on Circuits and Systems, ISCAS ; Conference date: 21-05-2023 Through 25-05-2023",

year = "2023",

doi = "10.1109/ISCAS46773.2023.10181619",

language = "English",

isbn = "978-1-6654-5110-9",

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address = "United States",

}

Monga, DC, Numan, O, Andraud, M & Halonen, K 2023, A temperature and process compensation circuit for resistive-based in-memory computing arrays. in ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. IEEE International Symposium on Circuits and Systems proceedings, vol. 2023-May, IEEE, IEEE International Symposium on Circuits and Systems, Monterey, California, United States, 21/05/2023. https://doi.org/10.1109/ISCAS46773.2023.10181619

A temperature and process compensation circuit for resistive-based in-memory computing arrays. / Monga, Dipesh C.; Numan, Omar; Andraud, Martin et al.
ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings. IEEE, 2023. (IEEE International Symposium on Circuits and Systems proceedings; Vol. 2023-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - A temperature and process compensation circuit for resistive-based in-memory computing arrays

AU - Monga, Dipesh C.

AU - Numan, Omar

AU - Andraud, Martin

AU - Halonen, Kari

N1 - Conference code: 56

PY - 2023

Y1 - 2023

N2 - In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.

AB - In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.

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KW - process compensation

KW - Resistive random access memory

KW - Thermal compensation

KW - ultra-low power

KW - variable temperature coefficient

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SN - 978-1-6654-5110-9

T3 - IEEE International Symposium on Circuits and Systems proceedings

BT - ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings

PB - IEEE

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 21 May 2023 through 25 May 2023

ER -

A temperature and process compensation circuit for resistive-based in-memory computing arrays

Abstract

Publication series

Conference

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

EHIR: Wireless impulse radio data link powered by energy harvesting

WHISTLE: When integrated systems gain life experience: towards self-learning circuits with resource-efficient embedded artificial intelligence

Cite this

A temperature and process compensation circuit for resistive-based in-memory computing arrays

Abstract

Publication series

Conference

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

Projects

EHIR: Wireless impulse radio data link powered by energy harvesting

WHISTLE: When integrated systems gain life experience: towards self-learning circuits with resource-efficient embedded artificial intelligence

Cite this