TY - JOUR
T1 - A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits
AU - Todri-Sanial, Aida
AU - Ramos, Raphael
AU - Okuno, Hanako
AU - Dijon, Jean
AU - Dhavamani, Abitha
AU - Wislicenus, Marcus
AU - Lilienthal, Katharina
AU - Uhlig, Benjamin
AU - Sadi, Toufik
AU - Georgiev, Vihar
AU - Asenov, Asen
AU - Amoroso, Salvatore
AU - Pender, Andrew
AU - Brown, Andrew
AU - Millar, Campbell
AU - Motzfeld, Fabian
AU - Gotsmann, Bernd
AU - Liang, Jie
AU - Gonçalves, Goncalo
AU - Rupesinghe, Nalin
AU - Teo, Ken
PY - 2017/4/1
Y1 - 2017/4/1
N2 - This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design.
AB - This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design.
UR - http://www.scopus.com/inward/record.url?scp=85019981923&partnerID=8YFLogxK
U2 - 10.1109/MCAS.2017.2689538
DO - 10.1109/MCAS.2017.2689538
M3 - Review Article
AN - SCOPUS:85019981923
VL - 17
SP - 47
EP - 62
JO - IEEE CIRCUITS AND SYSTEMS MAGAZINE
JF - IEEE CIRCUITS AND SYSTEMS MAGAZINE
SN - 1531-636X
IS - 2
M1 - 7932093
ER -