A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing

Omar Numan*, Martin Andraud, Kari Halonen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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Abstract

In-Memory Computing (IMC) accelerators based on resistive crossbars are emerging as a promising pathway toward improved energy efficiency in artificial neural networks. While significant research efforts are directed toward designing advanced resistive memory devices, the nonidealities associated with practical device implementation are often overlooked. Existing solutions typically compensate for these nonidealities during off-chip training, introducing additional complexities and failing to account for random errors such as noise, device failures, and cycle-to-cycle variability. To tackle this challenge, this work proposes a self-calibrated activation neuron topology that offers a fully online non-linearity compensation for IMC accelerators. The neuron merges multiply-accumulate operations with Rectified Linear Unit (ReLU) activation function in the analog domain for increased efficiency. The self-calibration is integrated into the data conversion process to minimize overheads and be fully online. The proposed activation neuron is designed and simulated using 22 nm FDSOI CMOS technology. The design demonstrates robustness across a wide temperature range (-40°C to 80°C) and under various process corners, with a maximum accuracy loss of 1 LSB for an 8-bit activation accuracy.

Original languageEnglish
Title of host publication2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023
PublisherIEEE
ISBN (Electronic)979-8-3503-2599-7
DOIs
Publication statusPublished - 2023
MoE publication typeA4 Conference publication
EventIEEE/IFIP International Conference on VLSI and System-on-Chip - Dubai, United Arab Emirates
Duration: 16 Oct 202318 Oct 2023
Conference number: 31

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Conference

ConferenceIEEE/IFIP International Conference on VLSI and System-on-Chip
Abbreviated titleVLSI-SoC
Country/TerritoryUnited Arab Emirates
CityDubai
Period16/10/202318/10/2023

Keywords

  • artificial neural networks
  • Edge AI
  • In-memory computing
  • on-chip PVT compensation
  • resistive cross-bars

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