A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

Mikko Englund; Kim B. Östman; Olli Viitala; Mikko Kaltiokallio; Kari Stadius; Kimmo Koli; Jussi Ryynänen

doi:10.1109/JSSC.2015.2397193

A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

Mikko Englund, Kim B. Östman, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Kimmo Koli, Jussi Ryynänen

Jussi Ryynänen Group

Research output: Contribution to journal › Article › Scientific › peer-review

32 Citations (Scopus)

Abstract

This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

Original language	English
Article number	7044615
Pages (from-to)	644-655
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	50
Issue number	3
DOIs	https://doi.org/10.1109/JSSC.2015.2397193
Publication status	Published - 1 Mar 2015
MoE publication type	A1 Journal article-refereed

Keywords

Blocker filtering
continuous-time
delta-sigma modulation
direct conversion receivers
direct delta-sigma receiver
frequency-translating
N-path filtering
noise shaping
RF sampling
wideband

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10.1109/JSSC.2015.2397193

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title = "A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS",

abstract = "This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.",

keywords = "Blocker filtering, continuous-time, delta-sigma modulation, direct conversion receivers, direct delta-sigma receiver, frequency-translating, N-path filtering, noise shaping, RF sampling, wideband",

author = "Mikko Englund and {\"O}stman, {Kim B.} and Olli Viitala and Mikko Kaltiokallio and Kari Stadius and Kimmo Koli and Jussi Ryyn{\"a}nen",

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AU - Englund, Mikko

AU - Östman, Kim B.

AU - Viitala, Olli

AU - Kaltiokallio, Mikko

AU - Stadius, Kari

AU - Koli, Kimmo

AU - Ryynänen, Jussi

PY - 2015/3/1

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N2 - This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

AB - This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

KW - Blocker filtering

KW - continuous-time

KW - delta-sigma modulation

KW - direct conversion receivers

KW - direct delta-sigma receiver

KW - frequency-translating

KW - N-path filtering

KW - noise shaping

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KW - wideband

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A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

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Keywords

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