A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

Mikko Englund; Kim B. Östman; Olli Viitala; Mikko Kaltiokallio; Kari Stadius; Kimmo Koli; Jussi Ryynänen

doi:10.1109/JSSC.2015.2397193

A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

Mikko Englund, Kim B. Östman, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Kimmo Koli, Jussi Ryynänen

Jussi Ryynänen Group

Research output: Contribution to journal › Article › Scientific › peer-review

31 Citations (Scopus)

Abstract

This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

Original language	English
Article number	7044615
Pages (from-to)	644-655
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	50
Issue number	3
DOIs	https://doi.org/10.1109/JSSC.2015.2397193
Publication status	Published - 1 Mar 2015
MoE publication type	A1 Journal article-refereed

Keywords

Blocker filtering
continuous-time
delta-sigma modulation
direct conversion receivers
direct delta-sigma receiver
frequency-translating
N-path filtering
noise shaping
RF sampling
wideband

Access to Document

10.1109/JSSC.2015.2397193

OpenUrl availability

Full text

Cite this

@article{b5a4343db073468396adf3b76d3732ba,

title = "A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS",

abstract = "This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.",

keywords = "Blocker filtering, continuous-time, delta-sigma modulation, direct conversion receivers, direct delta-sigma receiver, frequency-translating, N-path filtering, noise shaping, RF sampling, wideband",

author = "Mikko Englund and {\"O}stman, {Kim B.} and Olli Viitala and Mikko Kaltiokallio and Kari Stadius and Kimmo Koli and Jussi Ryyn{\"a}nen",

year = "2015",

month = mar,

day = "1",

doi = "10.1109/JSSC.2015.2397193",

language = "English",

volume = "50",

pages = "644--655",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "IEEE",

number = "3",

}

TY - JOUR

T1 - A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

AU - Englund, Mikko

AU - Östman, Kim B.

AU - Viitala, Olli

AU - Kaltiokallio, Mikko

AU - Stadius, Kari

AU - Koli, Kimmo

AU - Ryynänen, Jussi

PY - 2015/3/1

Y1 - 2015/3/1

N2 - This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

AB - This paper presents a wideband direct ΔΣ receiver for the 0.7-2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9-8.8 dB, and an IIP3 of -2 dBm.

KW - Blocker filtering

KW - continuous-time

KW - delta-sigma modulation

KW - direct conversion receivers

KW - direct delta-sigma receiver

KW - frequency-translating

KW - N-path filtering

KW - noise shaping

KW - RF sampling

KW - wideband

UR - http://www.scopus.com/inward/record.url?scp=84924336655&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2015.2397193

DO - 10.1109/JSSC.2015.2397193

M3 - Article

VL - 50

SP - 644

EP - 655

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 3

M1 - 7044615

ER -

A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS

Abstract

Keywords

Access to Document

OpenUrl availability

Other files and links

Fingerprint

Cite this