A Novel Technique for Noise Reduction in CMOS Subsamplers

S. Lindfors*, A. Parssinen, Jussi Ryynänen, K. Halonen

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    2 Citations (Scopus)

    Abstract

    The operation and design aspects of a receiver with a sub-sampling mixer are discussed at system level. A novel technique that improves the noise performance of CMOS sub-samplers is proposed. The sampling frequency with the proposed structure is fundamentally limited by the speed of the clock generator instead of the hold amplifier as is the case in previously reported subsamplers. A 300 MHz test sampler which is designed to be integrated together with a 1.8 GHz LNA is described.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    Editors Anon
    PublisherIEEE
    Pages257-260
    Number of pages4
    Volume1
    Publication statusPublished - 1998
    MoE publication typeA4 Article in a conference publication
    EventIEEE International Symposium on Circuits and Systems - Monterey, United States
    Duration: 31 May 19983 Jun 1998

    Publication series

    Namethe IEEE International Symposium on Circuits and Systems, 31 May - 3 June 1998, Monterey, USA
    NameIEEE International Symposium on Circuits and Systems
    ISSN (Print)0271-4302
    ISSN (Electronic)2158-1525

    Conference

    ConferenceIEEE International Symposium on Circuits and Systems
    Abbreviated titleISCAS
    CountryUnited States
    CityMonterey
    Period31/05/199803/06/1998

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