A low voltage 150Mbit/s transmitter and receiver circuit including a cable equalizer and clock recovery PFLL

K. Koli, K. Halonen, Jarkko Routama

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    Original languageEnglish
    Title of host publication15th NORCHIP Conference, Tallinn Estonia, 10-11 November 1997
    Pages289-295
    Publication statusPublished - 1997
    MoE publication typeA4 Article in a conference publication

    Keywords

    • cable equalizer
    • clock recovery
    • PFLL

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