A lightweight implementation of the Tav-128 hash function

Honorio Martin, Pedro Peris Lopez, Enrique San Millan, Juan E. Tapiador

Research output: Contribution to journalLetterScientificpeer-review

3 Citations (Scopus)


In this article we discuss the hardware implementation of a lightweight hash function, named Tav-128 [1], which was purposely designed for constrained devices such as low-cost RFID tags. In the original paper, the authors only provide an estimation of the hardware complexity. Motivated for this, we describe both an ASIC and an FPGA-based implementation of the aforementioned cryptographic primitive, and examine the performance of three architectures optimizing different criteria: area, throughput, and a trade-off between both of them.

Original languageEnglish
Article number20161255
Pages (from-to)1-9
Issue number11
Publication statusPublished - 2017
MoE publication typeA1 Journal article-refereed


  • ASIC
  • FPGA
  • Hardware implementation
  • Hash function

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