A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

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A digitally controlled 2.4-GHz oscillator in 65-nm CMOS. / Xu, Liangge; Lindfors, Saska; Stadius, Kari; Ryynänen, Jussi.

In: Analog Integrated Circuits and Signal Processing, Vol. 58, No. 1, 01.2009, p. 35-42.

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@article{38a7e9ca9c944151b1a46a7b153e7413,
title = "A digitally controlled 2.4-GHz oscillator in 65-nm CMOS",
abstract = "This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ∑Δ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is -122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.",
keywords = "Capacitance dithering, CMOS, DCO, Digital control, LC oscillator, LSB dithering, SDM, Sigma-delta modulator, Varactor bank",
author = "Liangge Xu and Saska Lindfors and Kari Stadius and Jussi Ryyn{\"a}nen",
year = "2009",
month = "1",
doi = "10.1007/s10470-008-9178-5",
language = "English",
volume = "58",
pages = "35--42",
journal = "Analog Integrated Circuits and Signal Processing",
issn = "0925-1030",
number = "1",

}

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TY - JOUR

T1 - A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

AU - Xu, Liangge

AU - Lindfors, Saska

AU - Stadius, Kari

AU - Ryynänen, Jussi

PY - 2009/1

Y1 - 2009/1

N2 - This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ∑Δ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is -122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.

AB - This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ∑Δ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is -122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.

KW - Capacitance dithering

KW - CMOS

KW - DCO

KW - Digital control

KW - LC oscillator

KW - LSB dithering

KW - SDM

KW - Sigma-delta modulator

KW - Varactor bank

UR - http://www.scopus.com/inward/record.url?scp=58049137714&partnerID=8YFLogxK

U2 - 10.1007/s10470-008-9178-5

DO - 10.1007/s10470-008-9178-5

M3 - Article

VL - 58

SP - 35

EP - 42

JO - Analog Integrated Circuits and Signal Processing

JF - Analog Integrated Circuits and Signal Processing

SN - 0925-1030

IS - 1

ER -

ID: 3246966