A digitally controlled 2.4-GHz oscillator in 65-nm CMOS
Research output: Contribution to journal › Article › Scientific › peer-review
This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ∑Δ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is -122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.
|Number of pages||8|
|Journal||Analog Integrated Circuits and Signal Processing|
|Publication status||Published - Jan 2009|
|MoE publication type||A1 Journal article-refereed|
- Capacitance dithering, CMOS, DCO, Digital control, LC oscillator, LSB dithering, SDM, Sigma-delta modulator, Varactor bank