A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Standard

A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators. / Olabode, Olaitan; Unnikrishnan, Vishnu; Kempi, Ilia; Hammer, Andreas; Kosunen, Marko; Ryynänen, Jussi.

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE, 2018. p. 1-4 8573454 (IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)).

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Olabode, O, Unnikrishnan, V, Kempi, I, Hammer, A, Kosunen, M & Ryynänen, J 2018, A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators. in 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)., 8573454, IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), IEEE, pp. 1-4, IEEE Nordic Circuits and Systems Conference, Tallinn, Estonia, 30/10/2018. https://doi.org/10.1109/NORCHIP.2018.8573454

APA

Olabode, O., Unnikrishnan, V., Kempi, I., Hammer, A., Kosunen, M., & Ryynänen, J. (2018). A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators. In 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) (pp. 1-4). [8573454] (IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)). IEEE. https://doi.org/10.1109/NORCHIP.2018.8573454

Vancouver

Olabode O, Unnikrishnan V, Kempi I, Hammer A, Kosunen M, Ryynänen J. A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators. In 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE. 2018. p. 1-4. 8573454. (IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)). https://doi.org/10.1109/NORCHIP.2018.8573454

Author

Olabode, Olaitan ; Unnikrishnan, Vishnu ; Kempi, Ilia ; Hammer, Andreas ; Kosunen, Marko ; Ryynänen, Jussi. / A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators. 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE, 2018. pp. 1-4 (IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)).

Bibtex - Download

@inproceedings{1f79e255096a4a5fb53f7cfbd3ee9ff2,
title = "A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators",
abstract = "This paper describes a configurable hysteresis comparator for asynchronous sigma-delta modulators (ASDM). The proposed comparator provides coarse and fine tuning options for configuring the loop delay and hence the frequency of an ASDM. The post-layout simulation of the comparator implemented in a 28 nm FDSOI process shows that the comparator provides hysteresis voltage range of ±(1 to 15.3) mV while consuming 36.8 nW to 4.4 uW from 0.7 V supply, which enables configurable ASDM center-frequency in the range of 100 kHz to 6 MHz.",
keywords = "configurable hysteresis, comparator, asynchronous, sigma-delta, modulator, ADC, Hysteresis;Delays;Tuning;Frequency modulation;Transistors;Power demand, CMOS, Low Power",
author = "Olaitan Olabode and Vishnu Unnikrishnan and Ilia Kempi and Andreas Hammer and Marko Kosunen and Jussi Ryyn{\"a}nen",
year = "2018",
month = "12",
day = "13",
doi = "10.1109/NORCHIP.2018.8573454",
language = "English",
isbn = "978-1-5386-7657-8",
series = "IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)",
publisher = "IEEE",
pages = "1--4",
booktitle = "2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)",
address = "United States",

}

RIS - Download

TY - GEN

T1 - A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators

AU - Olabode, Olaitan

AU - Unnikrishnan, Vishnu

AU - Kempi, Ilia

AU - Hammer, Andreas

AU - Kosunen, Marko

AU - Ryynänen, Jussi

PY - 2018/12/13

Y1 - 2018/12/13

N2 - This paper describes a configurable hysteresis comparator for asynchronous sigma-delta modulators (ASDM). The proposed comparator provides coarse and fine tuning options for configuring the loop delay and hence the frequency of an ASDM. The post-layout simulation of the comparator implemented in a 28 nm FDSOI process shows that the comparator provides hysteresis voltage range of ±(1 to 15.3) mV while consuming 36.8 nW to 4.4 uW from 0.7 V supply, which enables configurable ASDM center-frequency in the range of 100 kHz to 6 MHz.

AB - This paper describes a configurable hysteresis comparator for asynchronous sigma-delta modulators (ASDM). The proposed comparator provides coarse and fine tuning options for configuring the loop delay and hence the frequency of an ASDM. The post-layout simulation of the comparator implemented in a 28 nm FDSOI process shows that the comparator provides hysteresis voltage range of ±(1 to 15.3) mV while consuming 36.8 nW to 4.4 uW from 0.7 V supply, which enables configurable ASDM center-frequency in the range of 100 kHz to 6 MHz.

KW - configurable hysteresis, comparator, asynchronous, sigma-delta, modulator, ADC

KW - Hysteresis;Delays;Tuning;Frequency modulation;Transistors;Power demand, CMOS, Low Power

UR - https://ieeexplore.ieee.org/document/8573454

U2 - 10.1109/NORCHIP.2018.8573454

DO - 10.1109/NORCHIP.2018.8573454

M3 - Conference contribution

SN - 978-1-5386-7657-8

T3 - IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

SP - 1

EP - 4

BT - 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

PB - IEEE

ER -

ID: 30451736