A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators

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Abstract

This paper describes a configurable hysteresis comparator for asynchronous sigma-delta modulators (ASDM). The proposed comparator provides coarse and fine tuning options for configuring the loop delay and hence the frequency of an ASDM. The post-layout simulation of the comparator implemented in a 28 nm FDSOI process shows that the comparator provides hysteresis voltage range of ±(1 to 15.3) mV while consuming 36.8 nW to 4.4 uW from 0.7 V supply, which enables configurable ASDM center-frequency in the range of 100 kHz to 6 MHz.
Original languageEnglish
Title of host publication 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
PublisherIEEE
Pages1-4
Number of pages4
ISBN (Electronic)978-1-5386-7656-1
ISBN (Print)978-1-5386-7657-8
DOIs
Publication statusPublished - 13 Dec 2018
MoE publication typeA4 Article in a conference publication
EventIEEE Nordic Circuits and Systems Conference - Tallinn, Estonia
Duration: 30 Oct 201831 Oct 2018

Publication series

NameIEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
PublisherIEEE

Conference

ConferenceIEEE Nordic Circuits and Systems Conference
Abbreviated titleNORCAS
CountryEstonia
CityTallinn
Period30/10/201831/10/2018

Keywords

  • configurable hysteresis, comparator, asynchronous, sigma-delta, modulator, ADC
  • Hysteresis;Delays;Tuning;Frequency modulation;Transistors;Power demand, CMOS, Low Power

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