A Compact Untrimmed 48ppm/°C All MOS Current Reference Circuit

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Abstract

An ultra-low power and low-cost (area efficient) nano-Ampere current reference circuit designed in a 65 nm technology is presented in this paper: The proposed circuit is a resistorless beta multiplier current reference circuit that uses self cascode composite MOSFETs in triode region. Circuit analysis has been discussed in the paper. The simulated circuit consumes power of 550 nW at a nominal operating voltage of 1.33 V and occupies area of 0.0031 mm2. The design provides a line regulation of 1.9 %/V over an operating voltage range of 1.25 V to 1.4 V. Temperature coefficient (TC) of the circuit at nominal voltage of 1.33 V is 48 ppm/°C for a wide temperature range of-40°C to 85°C. Output current of the circuit at nominal voltage is 104.2 nA with a small process variation of only 4 %.

Original languageEnglish
Title of host publicationMWSCAS 2022 - 65th IEEE International Midwest Symposium on Circuits and Systems, Proceedings
PublisherIEEE
Number of pages5
ISBN (Electronic)978-1-6654-0279-8
DOIs
Publication statusPublished - 2022
MoE publication typeA4 Conference publication
EventInternational Midwest Symposium on Circuits and Systems - Fukuoka, Japan
Duration: 7 Aug 202210 Aug 2022
Conference number: 65

Publication series

NameConference proceedings : Midwest Symposium on Circuits and Systems
ISSN (Print)1548-3746
ISSN (Electronic)1558-3899

Conference

ConferenceInternational Midwest Symposium on Circuits and Systems
Abbreviated titleMWSCAS
Country/TerritoryJapan
CityFukuoka
Period07/08/202210/08/2022

Keywords

  • CMOS beta multiplier
  • Current reference
  • low temperature coefficient
  • low-power
  • self-cascode transistor

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