A common-gate common-source low noise amplifier based RF front end with selective input impedance matching for blocker-resilient receivers

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A common-gate common-source low noise amplifier based RF front end with selective input impedance matching for blocker-resilient receivers. / Ul Haq, Faizan; Östman, Kim B.; Englund, Mikko; Stadius, Kari; Kosunen, Marko; Koli, Kimmo; Ryynänen, Jussi.

In: International Journal of Circuit Theory and Applications, Vol. 46, No. 8, 08.2018, p. 1427-1442.

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@article{2fd8497b677a47a2ae94582a4949e12b,
title = "A common-gate common-source low noise amplifier based RF front end with selective input impedance matching for blocker-resilient receivers",
abstract = "This paper presents an integrated wideband radio frequency front end with improved blocker resilience achieved through selective voltage attenuation at both input and output nodes of the low noise amplifier (LNA). The architecture differs from traditional LNA architectures where blockers are only attenuated at LNA output node. The proposed dual attenuation is attained by designing a low intrinsic input impedance common-gate common-source LNA with capacitive feedback, together with an N-path filtering load. The capacitive feedback across the LNA ensures that the selective N-path filtering profile at the LNA output is transferred to the LNA input nodes creating a selective input impedance. Consequently, the achieved front-end input impedance is low at blocker frequencies and matched to the source impedance at the desired frequencies, creating the desired voltage attenuation for blockers. Further, a detailed theoretical analysis of proposed architecture is presented, which leads to clear design guidelines. Evaluated in a 28-nm fully depleted silicon-on-insulator complementary metal oxide semiconductor (CMOS) process, front end is designed for wideband operation from 0.7 to 2.7 GHz. It consumes 11-mA current from a 1-V supply (excluding local oscillator (LO) buffering) and possesses a maximum noise figure of 5.1 dB. The front end demonstrates an out-of-band blocker compression point of -1.5 dBm and out-of-band IIP3 of +14 dBm at a 100-MHz offset from LO frequency. In comparison with a traditional common-gate common-source LNA-based front end with wideband input impedance matching, the proposed front end achieves 3.5-dB improvement in the blocker compression point at a 100-MHz offset from LO.",
keywords = "Blocker tolerance, Low noise amplifier, RF front end, Selective impedance matching",
author = "{Ul Haq}, Faizan and {\"O}stman, {Kim B.} and Mikko Englund and Kari Stadius and Marko Kosunen and Kimmo Koli and Jussi Ryyn{\"a}nen",
year = "2018",
month = "8",
doi = "10.1002/cta.2473",
language = "English",
volume = "46",
pages = "1427--1442",
journal = "International Journal of Circuit Theory and Applications",
issn = "0098-9886",
publisher = "John Wiley and Sons Ltd",
number = "8",

}

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TY - JOUR

T1 - A common-gate common-source low noise amplifier based RF front end with selective input impedance matching for blocker-resilient receivers

AU - Ul Haq, Faizan

AU - Östman, Kim B.

AU - Englund, Mikko

AU - Stadius, Kari

AU - Kosunen, Marko

AU - Koli, Kimmo

AU - Ryynänen, Jussi

PY - 2018/8

Y1 - 2018/8

N2 - This paper presents an integrated wideband radio frequency front end with improved blocker resilience achieved through selective voltage attenuation at both input and output nodes of the low noise amplifier (LNA). The architecture differs from traditional LNA architectures where blockers are only attenuated at LNA output node. The proposed dual attenuation is attained by designing a low intrinsic input impedance common-gate common-source LNA with capacitive feedback, together with an N-path filtering load. The capacitive feedback across the LNA ensures that the selective N-path filtering profile at the LNA output is transferred to the LNA input nodes creating a selective input impedance. Consequently, the achieved front-end input impedance is low at blocker frequencies and matched to the source impedance at the desired frequencies, creating the desired voltage attenuation for blockers. Further, a detailed theoretical analysis of proposed architecture is presented, which leads to clear design guidelines. Evaluated in a 28-nm fully depleted silicon-on-insulator complementary metal oxide semiconductor (CMOS) process, front end is designed for wideband operation from 0.7 to 2.7 GHz. It consumes 11-mA current from a 1-V supply (excluding local oscillator (LO) buffering) and possesses a maximum noise figure of 5.1 dB. The front end demonstrates an out-of-band blocker compression point of -1.5 dBm and out-of-band IIP3 of +14 dBm at a 100-MHz offset from LO frequency. In comparison with a traditional common-gate common-source LNA-based front end with wideband input impedance matching, the proposed front end achieves 3.5-dB improvement in the blocker compression point at a 100-MHz offset from LO.

AB - This paper presents an integrated wideband radio frequency front end with improved blocker resilience achieved through selective voltage attenuation at both input and output nodes of the low noise amplifier (LNA). The architecture differs from traditional LNA architectures where blockers are only attenuated at LNA output node. The proposed dual attenuation is attained by designing a low intrinsic input impedance common-gate common-source LNA with capacitive feedback, together with an N-path filtering load. The capacitive feedback across the LNA ensures that the selective N-path filtering profile at the LNA output is transferred to the LNA input nodes creating a selective input impedance. Consequently, the achieved front-end input impedance is low at blocker frequencies and matched to the source impedance at the desired frequencies, creating the desired voltage attenuation for blockers. Further, a detailed theoretical analysis of proposed architecture is presented, which leads to clear design guidelines. Evaluated in a 28-nm fully depleted silicon-on-insulator complementary metal oxide semiconductor (CMOS) process, front end is designed for wideband operation from 0.7 to 2.7 GHz. It consumes 11-mA current from a 1-V supply (excluding local oscillator (LO) buffering) and possesses a maximum noise figure of 5.1 dB. The front end demonstrates an out-of-band blocker compression point of -1.5 dBm and out-of-band IIP3 of +14 dBm at a 100-MHz offset from LO frequency. In comparison with a traditional common-gate common-source LNA-based front end with wideband input impedance matching, the proposed front end achieves 3.5-dB improvement in the blocker compression point at a 100-MHz offset from LO.

KW - Blocker tolerance

KW - Low noise amplifier

KW - RF front end

KW - Selective impedance matching

UR - http://www.scopus.com/inward/record.url?scp=85046492444&partnerID=8YFLogxK

U2 - 10.1002/cta.2473

DO - 10.1002/cta.2473

M3 - Article

AN - SCOPUS:85046492444

VL - 46

SP - 1427

EP - 1442

JO - International Journal of Circuit Theory and Applications

JF - International Journal of Circuit Theory and Applications

SN - 0098-9886

IS - 8

ER -

ID: 21287279