A Charge Limiting and Redistribution Method for Delay Line Locking in Multi-Output Clock Generation

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review


Research units


This paper proposes a new type of delay line locking mechanism with digitally controlled charge transfer. Delay-locked loop (DLL) based on the presented method features multi-phase outputs and is stepwise driven towards lock by a co-action of 1-bit Time-to-Digital Converters and revised charge-pump. On-chip pulse “slicing” arrangement provides high-rate clock for the Digital Signal Processing algorithm, enabling fine-tuninig of the proposed DLL. Locking mechanism is implemented with standard digital cells and complete mixed-signal design is simulated in 28nm ST CMOS with full physical device models to prove functionality. When locked to reference frequency of 1.25GHz, this design consumes 1.1mW from 1V supply and produces 64+64 12ps-spaced output phases with <176fsPP phase error ripple and 50dB SFDR.


Original languageEnglish
Title of host publication2017 IEEE International Symposium on Circuits and Systems (ISCAS) Proceedings
Publication statusPublished - 28 Sep 2017
MoE publication typeA4 Article in a conference publication
EventIEEE International Symposium on Circuits and Systems - Marriot Waterfront, Baltimore, United States
Duration: 28 May 201731 May 2017

Publication series

NameIEEE International Symposium on Circuits and Systems proceedings
ISSN (Electronic)2379-447X


ConferenceIEEE International Symposium on Circuits and Systems
Abbreviated titleISCAS
CountryUnited States
Internet address

ID: 13439520