A Charge Limiting and Redistribution Method for Delay Line Locking in Multi-Output Clock Generation

Yury Antonov; Kari Stadius; Jussi Ryynänen

doi:10.1109/ISCAS.2017.8050740

A Charge Limiting and Redistribution Method for Delay Line Locking in Multi-Output Clock Generation

Yury Antonov, Kari Stadius, Jussi Ryynänen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

2 Citations (Scopus)

3 Downloads (Pure)

Abstract

This paper proposes a new type of delay line locking mechanism with digitally controlled charge transfer. Delay-locked loop (DLL) based on the presented method features multi-phase outputs and is stepwise driven towards lock by a co-action of 1-bit Time-to-Digital Converters and revised charge-pump. On-chip pulse “slicing” arrangement provides high-rate clock for the Digital Signal Processing algorithm, enabling fine-tuninig of the proposed DLL. Locking mechanism is implemented with standard digital cells and complete mixed-signal design is simulated in 28nm ST CMOS with full physical device models to prove functionality. When locked to reference frequency of 1.25GHz, this design consumes 1.1mW from 1V supply and produces 64+64 12ps-spaced output phases with <176fsPP phase error ripple and 50dB SFDR.

Original language	English
Title of host publication	2017 IEEE International Symposium on Circuits and Systems (ISCAS) Proceedings
Publisher	IEEE
Pages	1806-1809
ISBN (Electronic)	978-1-4673-6853-7
DOIs	https://doi.org/10.1109/ISCAS.2017.8050740
Publication status	Published - 28 Sep 2017
MoE publication type	A4 Article in a conference publication
Event	IEEE International Symposium on Circuits and Systems - Marriot Waterfront, Baltimore, United States Duration: 28 May 2017 → 31 May 2017 http://ieeexplore.ieee.org/document/8050249/

Publication series

Name	IEEE International Symposium on Circuits and Systems proceedings
ISSN (Electronic)	2379-447X

Conference

Conference	IEEE International Symposium on Circuits and Systems
Abbreviated title	ISCAS
Country/Territory	United States
City	Baltimore
Period	28/05/2017 → 31/05/2017
Internet address	http://ieeexplore.ieee.org/document/8050249/

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10.1109/ISCAS.2017.8050740

Antonov_Charge_Limiting_and_Redistribution_MethodAccepted author manuscript, 2.13 MB

Cite this

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title = "A Charge Limiting and Redistribution Method for Delay Line Locking in Multi-Output Clock Generation",

abstract = "This paper proposes a new type of delay line locking mechanism with digitally controlled charge transfer. Delay-locked loop (DLL) based on the presented method features multi-phase outputs and is stepwise driven towards lock by a co-action of 1-bit Time-to-Digital Converters and revised charge-pump. On-chip pulse “slicing” arrangement provides high-rate clock for the Digital Signal Processing algorithm, enabling fine-tuninig of the proposed DLL. Locking mechanism is implemented with standard digital cells and complete mixed-signal design is simulated in 28nm ST CMOS with full physical device models to prove functionality. When locked to reference frequency of 1.25GHz, this design consumes 1.1mW from 1V supply and produces 64+64 12ps-spaced output phases with <176fsPP phase error ripple and 50dB SFDR.",

author = "Yury Antonov and Kari Stadius and Jussi Ryyn{\"a}nen",

year = "2017",

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day = "28",

doi = "10.1109/ISCAS.2017.8050740",

language = "English",

series = "IEEE International Symposium on Circuits and Systems proceedings",

publisher = "IEEE",

pages = "1806--1809",

booktitle = "2017 IEEE International Symposium on Circuits and Systems (ISCAS) Proceedings",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems , ISCAS ; Conference date: 28-05-2017 Through 31-05-2017",

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Antonov, Y, Stadius, K & Ryynänen, J 2017, A Charge Limiting and Redistribution Method for Delay Line Locking in Multi-Output Clock Generation. in 2017 IEEE International Symposium on Circuits and Systems (ISCAS) Proceedings. IEEE International Symposium on Circuits and Systems proceedings, IEEE, pp. 1806-1809, IEEE International Symposium on Circuits and Systems , Baltimore, Maryland, United States, 28/05/2017. https://doi.org/10.1109/ISCAS.2017.8050740

A Charge Limiting and Redistribution Method for Delay Line Locking in Multi-Output Clock Generation. / Antonov, Yury; Stadius, Kari ; Ryynänen, Jussi.

2017 IEEE International Symposium on Circuits and Systems (ISCAS) Proceedings. IEEE, 2017. p. 1806-1809 (IEEE International Symposium on Circuits and Systems proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A Charge Limiting and Redistribution Method for Delay Line Locking in Multi-Output Clock Generation

AU - Antonov, Yury

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AU - Ryynänen, Jussi

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N2 - This paper proposes a new type of delay line locking mechanism with digitally controlled charge transfer. Delay-locked loop (DLL) based on the presented method features multi-phase outputs and is stepwise driven towards lock by a co-action of 1-bit Time-to-Digital Converters and revised charge-pump. On-chip pulse “slicing” arrangement provides high-rate clock for the Digital Signal Processing algorithm, enabling fine-tuninig of the proposed DLL. Locking mechanism is implemented with standard digital cells and complete mixed-signal design is simulated in 28nm ST CMOS with full physical device models to prove functionality. When locked to reference frequency of 1.25GHz, this design consumes 1.1mW from 1V supply and produces 64+64 12ps-spaced output phases with <176fsPP phase error ripple and 50dB SFDR.

AB - This paper proposes a new type of delay line locking mechanism with digitally controlled charge transfer. Delay-locked loop (DLL) based on the presented method features multi-phase outputs and is stepwise driven towards lock by a co-action of 1-bit Time-to-Digital Converters and revised charge-pump. On-chip pulse “slicing” arrangement provides high-rate clock for the Digital Signal Processing algorithm, enabling fine-tuninig of the proposed DLL. Locking mechanism is implemented with standard digital cells and complete mixed-signal design is simulated in 28nm ST CMOS with full physical device models to prove functionality. When locked to reference frequency of 1.25GHz, this design consumes 1.1mW from 1V supply and produces 64+64 12ps-spaced output phases with <176fsPP phase error ripple and 50dB SFDR.

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M3 - Conference contribution

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BT - 2017 IEEE International Symposium on Circuits and Systems (ISCAS) Proceedings

PB - IEEE

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 28 May 2017 through 31 May 2017

ER -

A Charge Limiting and Redistribution Method for Delay Line Locking in Multi-Output Clock Generation

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