A buffer size customization approach for application-specific NoC design

A. Chariete; M. Bakhouya; J. Gaber; M. Wack

doi:10.1109/HPCSim.2013.6641418

A buffer size customization approach for application-specific NoC design

A. Chariete, M. Bakhouya, J. Gaber, M. Wack

Department of Energy and Mechanical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

6 Citations (Scopus)

Abstract

In this paper, we present a design space exploration framework to allow the designer to customize a candidate on-chip interconnect architecture in order to match the application-specific workload in System-on-Chip. To show the benefit of using this methodology, a buffer space allocation algorithm is presented to allow designers to allocate only the required resource for each channel based on the traffic pattern of a target application. Simulations are conducted and results show that the proposed method achieves similar performance compared to the uniformly buffer space allocation method while using only 70% of resources budget.

Original language	English
Title of host publication	Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013
Pages	224-228
Number of pages	5
DOIs	https://doi.org/10.1109/HPCSim.2013.6641418
Publication status	Published - 2013
MoE publication type	A4 Conference publication
Event	International Conference on High Performance Computing & Simulation - Helsinki, Finland Duration: 1 Jul 2013 → 5 Jul 2013 Conference number: 11

Conference

Conference	International Conference on High Performance Computing & Simulation
Abbreviated title	HPCS
Country/Territory	Finland
City	Helsinki
Period	01/07/2013 → 05/07/2013

Keywords

Analytical Performance Evaluation
Design Space Exploration
Network-on-Chip
Simulation

Access to Document

10.1109/HPCSim.2013.6641418

Cite this

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title = "A buffer size customization approach for application-specific NoC design",

abstract = "In this paper, we present a design space exploration framework to allow the designer to customize a candidate on-chip interconnect architecture in order to match the application-specific workload in System-on-Chip. To show the benefit of using this methodology, a buffer space allocation algorithm is presented to allow designers to allocate only the required resource for each channel based on the traffic pattern of a target application. Simulations are conducted and results show that the proposed method achieves similar performance compared to the uniformly buffer space allocation method while using only 70% of resources budget.",

keywords = "Analytical Performance Evaluation, Design Space Exploration, Network-on-Chip, Simulation",

author = "A. Chariete and M. Bakhouya and J. Gaber and M. Wack",

year = "2013",

doi = "10.1109/HPCSim.2013.6641418",

language = "English",

isbn = "9781479908363",

pages = "224--228",

booktitle = "Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013",

note = "International Conference on High Performance Computing & Simulation, HPCS ; Conference date: 01-07-2013 Through 05-07-2013",

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Chariete, A, Bakhouya, M, Gaber, J & Wack, M 2013, A buffer size customization approach for application-specific NoC design. in Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013., 6641418, pp. 224-228, International Conference on High Performance Computing & Simulation, Helsinki, Finland, 01/07/2013. https://doi.org/10.1109/HPCSim.2013.6641418

A buffer size customization approach for application-specific NoC design. / Chariete, A.; Bakhouya, M.; Gaber, J. et al.
Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013. 2013. p. 224-228 6641418.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

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T1 - A buffer size customization approach for application-specific NoC design

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AU - Bakhouya, M.

AU - Gaber, J.

AU - Wack, M.

N1 - Conference code: 11

PY - 2013

Y1 - 2013

N2 - In this paper, we present a design space exploration framework to allow the designer to customize a candidate on-chip interconnect architecture in order to match the application-specific workload in System-on-Chip. To show the benefit of using this methodology, a buffer space allocation algorithm is presented to allow designers to allocate only the required resource for each channel based on the traffic pattern of a target application. Simulations are conducted and results show that the proposed method achieves similar performance compared to the uniformly buffer space allocation method while using only 70% of resources budget.

AB - In this paper, we present a design space exploration framework to allow the designer to customize a candidate on-chip interconnect architecture in order to match the application-specific workload in System-on-Chip. To show the benefit of using this methodology, a buffer space allocation algorithm is presented to allow designers to allocate only the required resource for each channel based on the traffic pattern of a target application. Simulations are conducted and results show that the proposed method achieves similar performance compared to the uniformly buffer space allocation method while using only 70% of resources budget.

KW - Analytical Performance Evaluation

KW - Design Space Exploration

KW - Network-on-Chip

KW - Simulation

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U2 - 10.1109/HPCSim.2013.6641418

DO - 10.1109/HPCSim.2013.6641418

M3 - Conference article in proceedings

AN - SCOPUS:84888021672

SN - 9781479908363

SP - 224

EP - 228

BT - Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013

T2 - International Conference on High Performance Computing & Simulation

Y2 - 1 July 2013 through 5 July 2013

ER -

A buffer size customization approach for application-specific NoC design

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