A buffer size customization approach for application-specific NoC design

A. Chariete, M. Bakhouya, J. Gaber, M. Wack

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

6 Citations (Scopus)

Abstract

In this paper, we present a design space exploration framework to allow the designer to customize a candidate on-chip interconnect architecture in order to match the application-specific workload in System-on-Chip. To show the benefit of using this methodology, a buffer space allocation algorithm is presented to allow designers to allocate only the required resource for each channel based on the traffic pattern of a target application. Simulations are conducted and results show that the proposed method achieves similar performance compared to the uniformly buffer space allocation method while using only 70% of resources budget.

Original languageEnglish
Title of host publicationProceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013
Pages224-228
Number of pages5
DOIs
Publication statusPublished - 2013
MoE publication typeA4 Article in a conference publication
EventInternational Conference on High Performance Computing & Simulation - Helsinki, Finland
Duration: 1 Jul 20135 Jul 2013
Conference number: 11

Conference

ConferenceInternational Conference on High Performance Computing & Simulation
Abbreviated titleHPCS
Country/TerritoryFinland
CityHelsinki
Period01/07/201305/07/2013

Keywords

  • Analytical Performance Evaluation
  • Design Space Exploration
  • Network-on-Chip
  • Simulation

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