A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Researchers

Research units

  • Huawei Technologies Oy
  • Nordic Semiconductor Oy

Abstract

SAW-less wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this paper, we introduce a blocker tolerant harmonic rejection RF front-end which is able to suppress blockers present at the local oscillator harmonics. The suppression is achieved by applying harmonic rejection in two stages, such that the first harmonic rejection already occurs at the output of LNA. The proposed front-end achieves this harmonic rejection with simpler 6-phase LO clocking and reduced number of base-band signal paths compared to 8-phase HR architectures. Further, the proposed design does not require any precise gain coefficients and implementing the harmonic rejection in two stages makes it more mismatch tolerant. In addition, near-band blocker linearity is improved by implementing a third order base-band feedback response which acts in conjunction with N-path filtering. Implemented in a 28nm FDSOI process, the front-end demonstrate 18-37dB harmonic rejection from the first stage and around 46-53dB of harmonic rejection from the second stage with a state-of-the-art blocker compression point of 2.5dBm for a third harmonic blocker and a near-band blocker compression point of -6.5dBm.

Details

Original languageEnglish
Title of host publicationIEEE Radio Frequency Integrated Circuits Symposium
Publication statusAccepted/In press - 3 Jun 2019
MoE publication typeA4 Article in a conference publication
EventIEEE Radio Frequency Integrated Circuits Symposium - Boston convocation center, Boston, United States
Duration: 2 Jun 20194 Jun 2019
https://www.rfic-ieee.org/

Publication series

NameIEEE Radio Frequency Integrated Circuits Symposium digest of papers
ISSN (Print)1529-2517
ISSN (Electronic)2375-0995

Conference

ConferenceIEEE Radio Frequency Integrated Circuits Symposium
Abbreviated titleRFIC
CountryUnited States
CityBoston
Period02/06/201904/06/2019
Internet address

    Research areas

  • Harmonic rejection, blocker tolerance

ID: 35822005