A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End

Faizan Ul Haq; Mikko Englund; Yury Antonov; Kari Stadius; Marko Kosunen; Kim Östman; Kimmo Koli; Jussi Ryynänen

doi:10.1109/RFIC.2019.8701765

A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End

Faizan Ul Haq, Mikko Englund, Yury Antonov, Kari Stadius, Marko Kosunen, Kim Östman, Kimmo Koli, Jussi Ryynänen

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

5 Citations (Scopus)

195 Downloads (Pure)

Abstract

SAW-less wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this paper, we introduce a blocker tolerant harmonic rejection RF front-end which is able to suppress blockers present at the local oscillator harmonics. The suppression is achieved by applying harmonic rejection in two stages, such that the first harmonic rejection already occurs at the output of LNA. The proposed front-end achieves this harmonic rejection with simpler 6-phase LO clocking and reduced number of base-band signal paths compared to 8-phase HR architectures. Further, the proposed design does not require any precise gain coefficients and implementing the harmonic rejection in two stages makes it more mismatch tolerant. In addition, near-band blocker linearity is improved by implementing a third order base-band feedback response which acts in conjunction with N-path filtering. Implemented in a 28nm FDSOI process, the front-end demonstrate 18-37dB harmonic rejection from the first stage and around 46-53dB of harmonic rejection from the second stage with a state-of-the-art blocker compression point of 2.5dBm for a third harmonic blocker and a near-band blocker compression point of -6.5dBm.

Original language	English
Title of host publication	IEEE Radio Frequency Integrated Circuits Symposium
Publisher	IEEE
Pages	203-206
ISBN (Electronic)	978-1-7281-1701-0
DOIs	https://doi.org/10.1109/RFIC.2019.8701765
Publication status	Published - 2019
MoE publication type	A4 Conference publication
Event	IEEE Radio Frequency Integrated Circuits Symposium - Boston convocation center, Boston, United States Duration: 2 Jun 2019 → 4 Jun 2019 https://www.rfic-ieee.org/

Publication series

Name	IEEE Radio Frequency Integrated Circuits Symposium digest of papers
ISSN (Print)	1529-2517
ISSN (Electronic)	2375-0995

Conference

Conference	IEEE Radio Frequency Integrated Circuits Symposium
Abbreviated title	RFIC
Country/Territory	United States
City	Boston
Period	02/06/2019 → 04/06/2019
Internet address	https://www.rfic-ieee.org/

Keywords

Harmonic rejection
blocker tolerance

Access to Document

10.1109/RFIC.2019.8701765

ELEC_UlHaq_Blocker-tolerant_RFICSAccepted author manuscript, 1.37 MB

ADVANTAG5: Advanced Wide-Band Transceiver Architectures for Beyond 5G Wireless Systems
Kosunen, M. (Principal investigator)
01/05/2017 → 30/06/2020
Project: EU: Framework programmes funding

Cite this

@inproceedings{60f8f5dcda1d43ee8ddfe51206446ac7,

title = "A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End",

abstract = "SAW-less wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this paper, we introduce a blocker tolerant harmonic rejection RF front-end which is able to suppress blockers present at the local oscillator harmonics. The suppression is achieved by applying harmonic rejection in two stages, such that the first harmonic rejection already occurs at the output of LNA. The proposed front-end achieves this harmonic rejection with simpler 6-phase LO clocking and reduced number of base-band signal paths compared to 8-phase HR architectures. Further, the proposed design does not require any precise gain coefficients and implementing the harmonic rejection in two stages makes it more mismatch tolerant. In addition, near-band blocker linearity is improved by implementing a third order base-band feedback response which acts in conjunction with N-path filtering. Implemented in a 28nm FDSOI process, the front-end demonstrate 18-37dB harmonic rejection from the first stage and around 46-53dB of harmonic rejection from the second stage with a state-of-the-art blocker compression point of 2.5dBm for a third harmonic blocker and a near-band blocker compression point of -6.5dBm.",

keywords = "Harmonic rejection, blocker tolerance",

author = "{Ul Haq}, Faizan and Mikko Englund and Yury Antonov and Kari Stadius and Marko Kosunen and Kim {\"O}stman and Kimmo Koli and Jussi Ryyn{\"a}nen",

note = "| openaire: EC/H2020/704947/EU//ADVANTAG5; IEEE Radio Frequency Integrated Circuits Symposium, RFIC ; Conference date: 02-06-2019 Through 04-06-2019",

year = "2019",

doi = "10.1109/RFIC.2019.8701765",

language = "English",

series = "IEEE Radio Frequency Integrated Circuits Symposium digest of papers",

publisher = "IEEE",

pages = "203--206",

booktitle = "IEEE Radio Frequency Integrated Circuits Symposium",

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}

Ul Haq, F, Englund, M, Antonov, Y, Stadius, K , Kosunen, M, Östman, K, Koli, K & Ryynänen, J 2019, A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End. in IEEE Radio Frequency Integrated Circuits Symposium. IEEE Radio Frequency Integrated Circuits Symposium digest of papers, IEEE, pp. 203-206, IEEE Radio Frequency Integrated Circuits Symposium, Boston, Massachusetts, United States, 02/06/2019. https://doi.org/10.1109/RFIC.2019.8701765

A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End. / Ul Haq, Faizan; Englund, Mikko; Antonov, Yury et al.
IEEE Radio Frequency Integrated Circuits Symposium. IEEE, 2019. p. 203-206 (IEEE Radio Frequency Integrated Circuits Symposium digest of papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End

AU - Ul Haq, Faizan

AU - Englund, Mikko

AU - Antonov, Yury

AU - Stadius, Kari

AU - Kosunen, Marko

AU - Östman, Kim

AU - Koli, Kimmo

AU - Ryynänen, Jussi

N1 - | openaire: EC/H2020/704947/EU//ADVANTAG5

PY - 2019

Y1 - 2019

N2 - SAW-less wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this paper, we introduce a blocker tolerant harmonic rejection RF front-end which is able to suppress blockers present at the local oscillator harmonics. The suppression is achieved by applying harmonic rejection in two stages, such that the first harmonic rejection already occurs at the output of LNA. The proposed front-end achieves this harmonic rejection with simpler 6-phase LO clocking and reduced number of base-band signal paths compared to 8-phase HR architectures. Further, the proposed design does not require any precise gain coefficients and implementing the harmonic rejection in two stages makes it more mismatch tolerant. In addition, near-band blocker linearity is improved by implementing a third order base-band feedback response which acts in conjunction with N-path filtering. Implemented in a 28nm FDSOI process, the front-end demonstrate 18-37dB harmonic rejection from the first stage and around 46-53dB of harmonic rejection from the second stage with a state-of-the-art blocker compression point of 2.5dBm for a third harmonic blocker and a near-band blocker compression point of -6.5dBm.

AB - SAW-less wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this paper, we introduce a blocker tolerant harmonic rejection RF front-end which is able to suppress blockers present at the local oscillator harmonics. The suppression is achieved by applying harmonic rejection in two stages, such that the first harmonic rejection already occurs at the output of LNA. The proposed front-end achieves this harmonic rejection with simpler 6-phase LO clocking and reduced number of base-band signal paths compared to 8-phase HR architectures. Further, the proposed design does not require any precise gain coefficients and implementing the harmonic rejection in two stages makes it more mismatch tolerant. In addition, near-band blocker linearity is improved by implementing a third order base-band feedback response which acts in conjunction with N-path filtering. Implemented in a 28nm FDSOI process, the front-end demonstrate 18-37dB harmonic rejection from the first stage and around 46-53dB of harmonic rejection from the second stage with a state-of-the-art blocker compression point of 2.5dBm for a third harmonic blocker and a near-band blocker compression point of -6.5dBm.

KW - Harmonic rejection

KW - blocker tolerance

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DO - 10.1109/RFIC.2019.8701765

M3 - Conference article in proceedings

T3 - IEEE Radio Frequency Integrated Circuits Symposium digest of papers

SP - 203

EP - 206

BT - IEEE Radio Frequency Integrated Circuits Symposium

PB - IEEE

T2 - IEEE Radio Frequency Integrated Circuits Symposium

Y2 - 2 June 2019 through 4 June 2019

ER -

A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End

Abstract

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Projects

ADVANTAG5: Advanced Wide-Band Transceiver Architectures for Beyond 5G Wireless Systems

Cite this