A 60-GHz CMOS receiver with an on-chip ADC

Mikko Varonen; Mikko Kaltiokallio; Ville Saari; Olli Viitala; Mikko Kärkkäinen; Saska Lindfors; Jussi Ryynänen; Kari A I Halonen

doi:10.1109/RFIC.2009.5135577

A 60-GHz CMOS receiver with an on-chip ADC

Mikko Varonen^*
, Mikko Kaltiokallio
, Ville Saari
, Olli Viitala
, Mikko Kärkkäinen
, Saska Lindfors
, Jussi Ryynänen
, Kari A I Halonen

^*Corresponding author for this work

Texas Instruments

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

20 Citations (Scopus)

Abstract

A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is -38.5 dBm.

Original language	English
Title of host publication	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Pages	445-448
Number of pages	4
DOIs	https://doi.org/10.1109/RFIC.2009.5135577
Publication status	Published - 2009
MoE publication type	A4 Conference publication
Event	IEEE Radio Frequency Integrated Circuits Symposium - Boston, United States Duration: 7 Jun 2009 → 9 Jun 2009

Conference

Conference	IEEE Radio Frequency Integrated Circuits Symposium
Abbreviated title	RFIC
Country/Territory	United States
City	Boston
Period	07/06/2009 → 09/06/2009

Keywords

ADC
CMOS
MMIC receivers

Access to Document

10.1109/RFIC.2009.5135577

Cite this

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title = "A 60-GHz CMOS receiver with an on-chip ADC",

abstract = "A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is -38.5 dBm.",

keywords = "ADC, CMOS, MMIC receivers",

author = "Mikko Varonen and Mikko Kaltiokallio and Ville Saari and Olli Viitala and Mikko K{\"a}rkk{\"a}inen and Saska Lindfors and Jussi Ryyn{\"a}nen and Halonen, \{Kari A I\}",

year = "2009",

doi = "10.1109/RFIC.2009.5135577",

language = "English",

isbn = "9781424433780",

pages = "445--448",

booktitle = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",

note = "IEEE Radio Frequency Integrated Circuits Symposium, RFIC ; Conference date: 07-06-2009 Through 09-06-2009",

}

Varonen, M, Kaltiokallio, M, Saari, V, Viitala, O, Kärkkäinen, M, Lindfors, S, Ryynänen, J & Halonen, KAI 2009, A 60-GHz CMOS receiver with an on-chip ADC. in Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium., 5135577, pp. 445-448, IEEE Radio Frequency Integrated Circuits Symposium, Boston, Massachusetts, United States, 07/06/2009. https://doi.org/10.1109/RFIC.2009.5135577

TY - GEN

T1 - A 60-GHz CMOS receiver with an on-chip ADC

AU - Varonen, Mikko

AU - Kaltiokallio, Mikko

AU - Saari, Ville

AU - Viitala, Olli

AU - Kärkkäinen, Mikko

AU - Lindfors, Saska

AU - Ryynänen, Jussi

AU - Halonen, Kari A I

PY - 2009

Y1 - 2009

N2 - A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is -38.5 dBm.

AB - A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is -38.5 dBm.

KW - ADC

KW - CMOS

KW - MMIC receivers

UR - https://www.scopus.com/pages/publications/70350230270

U2 - 10.1109/RFIC.2009.5135577

DO - 10.1109/RFIC.2009.5135577

M3 - Conference article in proceedings

AN - SCOPUS:70350230270

SN - 9781424433780

SP - 445

EP - 448

BT - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

T2 - IEEE Radio Frequency Integrated Circuits Symposium

Y2 - 7 June 2009 through 9 June 2009

ER -

A 60-GHz CMOS receiver with an on-chip ADC

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Keywords

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