A 60-GHz CMOS receiver with an on-chip ADC

Mikko Varonen*, Mikko Kaltiokallio, Ville Saari, Olli Viitala, Mikko Kärkkäinen, Saska Lindfors, Jussi Ryynänen, Kari A I Halonen

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    17 Citations (Scopus)


    A broadband 60-GHz receiver implemented in a 65-nm baseline CMOS technology is presented. A millimeter-wave front-end, including a single-ended low noise amplifier and a balanced resistive mixer, an IF-stage and an analog baseband circuit with an analog-to-digital converter are integrated on a single chip. The receiver achieves a measured 7.0-dB noise figure at 60 GHz and the voltage gain can be controlled between 45 to 79 dB. The measured 1-dB input compression point is -38.5 dBm.

    Original languageEnglish
    Title of host publicationDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
    Number of pages4
    Publication statusPublished - 2009
    MoE publication typeA4 Article in a conference publication
    EventIEEE Radio Frequency Integrated Circuits Symposium - Boston, United States
    Duration: 7 Jun 20099 Jun 2009


    ConferenceIEEE Radio Frequency Integrated Circuits Symposium
    Abbreviated titleRFIC
    CountryUnited States


    • ADC
    • CMOS
    • MMIC receivers

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