A 5.8-Gbps low-noise scalable low-voltage signaling serial link transmitter for MIPI M-PHY in 40-nm CMOS
Research output: Contribution to journal › Article › Scientific › peer-review
A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200–400 mV pp signals at date rates of 1.25–5.8 Gbps. The integrated circuit entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm2, while the actual driver occupies only 190 μm2. In this work it was confirmed that a low-power SLVS driver meets the stringent common-mode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below −138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS pre-drivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44–1.4 mW/Gbps with external clock and 2.6–4.7 mW/Gbps with clock synthesizer.
|Number of pages||11|
|Journal||Analog Integrated Circuits and Signal Processing|
|Publication status||Published - 2015|
|MoE publication type||A1 Journal article-refereed|
- All-digital phase-locked loop (ADPLL), CMOS, Low-drop-out voltage regulator (LDO), M-PHY, Mobile Industry Processor Interface (MIPI), Scalable low voltage signaling (SLVS)