Abstract
This paper describes the design and post-layout simulations of a 2/3/4- modulus frequency divider circuit, accompanied with an accumulator that controls the division count. The circuit is capable of operating as an integer or as a fractional divider. Key topic of this paper is the merging of div-2/3 and div-3/4 circuits into a single compact circuit that solves an issue of a forbidden state in fractional-division operation. The circuit is designed with 28-nm CMOS technology and the post-layout simulations indicate an operating input frequency range of 0.3 - 5.4 GHz with 13-bit fractional frequency resolution between division ratios of 2-4. The divider occupies only 40 µm x 30 µm while consuming 2.0 mW at 5.4 GHz input frequency.
| Original language | English |
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| Title of host publication | 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings |
| Publisher | IEEE |
| Number of pages | 5 |
| ISBN (Electronic) | 978-1-7281-9201-7 |
| DOIs | |
| Publication status | Published - 2021 |
| MoE publication type | A4 Conference publication |
| Event | IEEE International Symposium on Circuits and Systems - Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021 Conference number: 53 |
Publication series
| Name | IEEE International Symposium on Circuits and Systems proceedings |
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| ISSN (Print) | 0271-4302 |
| ISSN (Electronic) | 2158-1525 |
Conference
| Conference | IEEE International Symposium on Circuits and Systems |
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| Abbreviated title | ISCAS |
| Country/Territory | Korea, Republic of |
| City | Daegu |
| Period | 22/05/2021 → 28/05/2021 |
Keywords
- CMOS
- Frequency division
- Frequency synthesis
- RFIC