A 5.3 pJ/op approximate TTA VLIW tailored for machine learning

Jukka Teittinen*, Markus Hiienkari, Indre Zliobaite, Jaakko Hollmen, Heikki Berg, Juha Heiskala, Timo Viitanen, Jesse Simonsson, Lauri Koskinen

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

2 Citations (Scopus)

Abstract

To achieve energy efficiency in the Internet-of-Things (IoT), more intelligence is required in the wireless IoT nodes. Otherwise, the energy required by the wireless communication of raw sensor data will prohibit battery lifetime, the backbone of IoT. One option to achive this intelligence is to implement a variety of machine learning algorithms on the IoT sensor instead of the cloud. Shown here is sub-milliwatt machine learning accelerator operating at the Ultra-Low Voltage Minimum-Energy Point. The accelerator is a Transport Triggered Architecture (TTA) Application-Specific Instruction-Set Processor (ASIP) targeted for running various Machine Learning algorithms. The ASIP is implemented in 28 nm FDSOI (Fully Depleted Silicon On Insulator) CMOS process, with an operating voltage of 0.35 V, and is capable of 5.3pJ/cycle and 1.8nJ/iteration when performing conventional machine learning algorithms. The ASIP also includes hardware and compiler support for approximate computing. With the machine learning algorithms, computing approximately brings a maximum of 4.7% energy savings.

Original languageEnglish
Pages (from-to)106-113
Number of pages8
JournalMicroelectronics Journal
Volume61
DOIs
Publication statusPublished - 1 Mar 2017
MoE publication typeA1 Journal article-refereed

Keywords

  • Approximate computing
  • Integrated circuit
  • Machine learning
  • Minimum energy point
  • Processor
  • Timing error detection

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