A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS

Research output: Contribution to journalArticleScientificpeer-review

Researchers

Research units

Abstract

This paper presents a fully integrated 40-GHz transceiver designed for 2 Gbit/s short-range chip-to-chip communication link. The proposed architecture includes both the transmitter and the receiver and is optimized for on–off-keying modulation scheme. The transceiver design includes two variants, which can drive either a planar on-chip antenna or wire-bonded off-chip antenna. The performance comparison of these is given in the paper. A compact and energy-efficient technique has been adopted by directly modulating the oscillator in the transmitter. The receiver uses a self-mixing topology followed by transimpedance amplifier and a limiter chain. The detailed circuit descriptions as well as design trade-offs with simulation results in 65 nm CMOS are given. In addition, an example design modification to extend the modulation to 4-level amplitude shift keying is presented.

Details

Original languageEnglish
Pages (from-to)23-33
Number of pages11
JournalAnalog Integrated Circuits and Signal Processing
Volume83
Issue number1
Publication statusPublished - 6 Feb 2015
MoE publication typeA1 Journal article-refereed

    Research areas

  • CMOS, On–off-keying, Transceiver design, Wireless link

ID: 1976526