A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Mikko Kaltiokallio, Jani Mäkipää, Arto Rantala, Matti Sopanen

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

9 Citations (Scopus)


The increased performance from technology scaling makes it feasible to operate digital circuits at ultra-low voltages without the significant performance limitation of earlier process generations. The theoretical minimum energy point resides in near-threshold voltages in current processes, but device and environment variations make it a challenge to operate the circuits reliably. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS employing timing-error prevention with clock stretching to enable it to operate with minimal safety margins while maximizing energy efficiency. Measurements show 3.15pJ/cyc energy consumption at 400mV/2.4MHz, which corresponds to 39% energy savings and 83% EDP reduction compared to operation based on static signoff timing.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
ISBN (Electronic)9781479932863
Publication statusPublished - 4 Nov 2014
MoE publication typeA4 Article in a conference publication
EventIEEE Custom Integrated Circuits Conference: The Showcase for Integrated Circuit Design in the Heart of Silicon Valley - San Jose, United States
Duration: 15 Sep 201417 Sep 2014
Conference number: 36


ConferenceIEEE Custom Integrated Circuits Conference
Abbreviated titleCiCC
CountryUnited States
CitySan Jose


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