A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Researchers

Research units

  • Ericsson Oy

Abstract

This paper presents a 2.5-GHz RF-to-digital converter implemented in a 40-nm CMOS technology. The architecture embeds a direct-conversion receiver RF front-end in a 1.5-bit continuous-time ΔΣ modulator loop. This allows simultaneous channel filtering and noise shaping that begins already in the RF stages. The implemented design pays particular attention to the frequency-translating interface at the LNA output, where a programmable impedance enables a tradeoff between receiver sensitivity and maximum SNDR. The receiver consumes 90 mW from 1.1 V, and achieves a state-of-the-art noise figure (NF) of 4.2 dB and 50-dB peak SNDR for a 15-MHz RF bandwidth.

Details

Original languageEnglish
Title of host publicationESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
Publication statusPublished - 31 Oct 2014
MoE publication typeA4 Article in a conference publication
EventEuropean Solid-State Circuits Conference - Venezia Lido, Italy
Duration: 22 Sep 201426 Sep 2014
Conference number: 40

Conference

ConferenceEuropean Solid-State Circuits Conference
Abbreviated titleESSCIRC
CountryItaly
CityVenezia Lido
Period22/09/201426/09/2014

ID: 3245745