A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator

Mikko Englund; Kim B. Östman; Olli Viitala; Mikko Kaltiokallio; Kari Stadius; Jussi Ryynänen; Kimmo Koli

doi:10.1109/ESSCIRC.2014.6942099

A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator

Mikko Englund^*, Kim B. Östman, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Jussi Ryynänen, Kimmo Koli

^*Corresponding author for this work

Jussi Ryynänen Group

Ericsson Oy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

2 Citations (Scopus)

Abstract

This paper presents a 2.5-GHz RF-to-digital converter implemented in a 40-nm CMOS technology. The architecture embeds a direct-conversion receiver RF front-end in a 1.5-bit continuous-time ΔΣ modulator loop. This allows simultaneous channel filtering and noise shaping that begins already in the RF stages. The implemented design pays particular attention to the frequency-translating interface at the LNA output, where a programmable impedance enables a tradeoff between receiver sensitivity and maximum SNDR. The receiver consumes 90 mW from 1.1 V, and achieves a state-of-the-art noise figure (NF) of 4.2 dB and 50-dB peak SNDR for a 15-MHz RF bandwidth.

Original language	English
Title of host publication	ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
Publisher	IEEE
Pages	371-374
Number of pages	4
ISBN (Print)	9781479956944
DOIs	https://doi.org/10.1109/ESSCIRC.2014.6942099
Publication status	Published - 31 Oct 2014
MoE publication type	A4 Article in a conference publication
Event	European Solid-State Circuits Conference - Venezia Lido, Italy Duration: 22 Sept 2014 → 26 Sept 2014 Conference number: 40

Conference

Conference	European Solid-State Circuits Conference
Abbreviated title	ESSCIRC
Country/Territory	Italy
City	Venezia Lido
Period	22/09/2014 → 26/09/2014

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@inproceedings{72bc7ad514c94516967d40cfdaf46e02,

title = "A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator",

abstract = "This paper presents a 2.5-GHz RF-to-digital converter implemented in a 40-nm CMOS technology. The architecture embeds a direct-conversion receiver RF front-end in a 1.5-bit continuous-time ΔΣ modulator loop. This allows simultaneous channel filtering and noise shaping that begins already in the RF stages. The implemented design pays particular attention to the frequency-translating interface at the LNA output, where a programmable impedance enables a tradeoff between receiver sensitivity and maximum SNDR. The receiver consumes 90 mW from 1.1 V, and achieves a state-of-the-art noise figure (NF) of 4.2 dB and 50-dB peak SNDR for a 15-MHz RF bandwidth.",

author = "Mikko Englund and {\"O}stman, {Kim B.} and Olli Viitala and Mikko Kaltiokallio and Kari Stadius and Jussi Ryyn{\"a}nen and Kimmo Koli",

year = "2014",

month = oct,

day = "31",

doi = "10.1109/ESSCIRC.2014.6942099",

language = "English",

isbn = "9781479956944",

pages = "371--374",

booktitle = "ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference",

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Englund, M, Östman, KB, Viitala, O, Kaltiokallio, M, Stadius, K , Ryynänen, J & Koli, K 2014, A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator. in ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference., 6942099, IEEE, pp. 371-374, European Solid-State Circuits Conference, Venezia Lido, Italy, 22/09/2014. https://doi.org/10.1109/ESSCIRC.2014.6942099

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T1 - A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator

AU - Englund, Mikko

AU - Östman, Kim B.

AU - Viitala, Olli

AU - Kaltiokallio, Mikko

AU - Stadius, Kari

AU - Ryynänen, Jussi

AU - Koli, Kimmo

N1 - Conference code: 40

PY - 2014/10/31

Y1 - 2014/10/31

N2 - This paper presents a 2.5-GHz RF-to-digital converter implemented in a 40-nm CMOS technology. The architecture embeds a direct-conversion receiver RF front-end in a 1.5-bit continuous-time ΔΣ modulator loop. This allows simultaneous channel filtering and noise shaping that begins already in the RF stages. The implemented design pays particular attention to the frequency-translating interface at the LNA output, where a programmable impedance enables a tradeoff between receiver sensitivity and maximum SNDR. The receiver consumes 90 mW from 1.1 V, and achieves a state-of-the-art noise figure (NF) of 4.2 dB and 50-dB peak SNDR for a 15-MHz RF bandwidth.

AB - This paper presents a 2.5-GHz RF-to-digital converter implemented in a 40-nm CMOS technology. The architecture embeds a direct-conversion receiver RF front-end in a 1.5-bit continuous-time ΔΣ modulator loop. This allows simultaneous channel filtering and noise shaping that begins already in the RF stages. The implemented design pays particular attention to the frequency-translating interface at the LNA output, where a programmable impedance enables a tradeoff between receiver sensitivity and maximum SNDR. The receiver consumes 90 mW from 1.1 V, and achieves a state-of-the-art noise figure (NF) of 4.2 dB and 50-dB peak SNDR for a 15-MHz RF bandwidth.

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DO - 10.1109/ESSCIRC.2014.6942099

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AN - SCOPUS:84909955949

SN - 9781479956944

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BT - ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference

PB - IEEE

T2 - European Solid-State Circuits Conference

Y2 - 22 September 2014 through 26 September 2014

ER -

A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator

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