A 2.4-GHz Low-Power All-Digital Phase-Locked Loop

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Original languageEnglish
Pages (from-to)1513-1521
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number8
Publication statusPublished - 2010
MoE publication typeA1 Journal article-refereed

    Research areas

  • ADPLL, DCO, frequency synthesis, ISM band, low power, TDC, variable phase accumulator

ID: 941358