A 2.4-GHz Low-Power All-Digital Phase-Locked Loop

Liangge Xu, Saska Lindfors, Kari Stadius, Jussi Ryynänen

Research output: Contribution to journalArticleScientificpeer-review

45 Citations (Scopus)
Original languageEnglish
Pages (from-to)1513-1521
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number8
DOIs
Publication statusPublished - 2010
MoE publication typeA1 Journal article-refereed

Keywords

  • ADPLL
  • DCO
  • frequency synthesis
  • ISM band
  • low power
  • TDC
  • variable phase accumulator

Cite this