Projects per year
Abstract
Deep neural network (DNN) accelerators are increasingly integrated into sensing applications, such as wearables and sensor networks, to provide advanced in-sensor processing capabilities. Given wearables' strict size and power requirements, minimizing the area and energy consumption of DNN accelerators is a critical concern. In that regard, computing DNN models in the time domain is a promising architecture, taking advantage of both technology scaling friendliness and efficiency. Yet, time-domain accelerators are typically not fully digital, limiting the full benefits of time-domain computation. In this work, we propose an all-digital time-domain accelerator with a small size and low energy consumption to target precision in-sensor processing like human activity recognition (HAR). The proposed accelerator features a simple and efficient architecture without dependencies on analog nonidealities such as leakage and charge errors. An eight-neuron layer (core computation layer) is implemented in 22-nm FD-SOI technology. The layer occupies 70 × 70 μ m while supporting multibit inputs (8-bit) and weights (8-bit) with signed accumulation up to 18 bits. The power dissipation of the computation layer is 576 μ W at 0.72-V supply and 500-MHz clock frequency achieving an average area efficiency of 24.74 GOPS/mm 2 (up to 544.22 GOPS/mm 2 ), an average energy efficiency of 0.21 TOPS/W (up to 4.63 TOPS/W), and a normalized energy efficiency of 13.46 1b-TOPS/W (up to 296.30 1b-TOPS/W).
| Original language | English |
|---|---|
| Article number | 10758340 |
| Pages (from-to) | 2220-2231 |
| Number of pages | 12 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 32 |
| Issue number | 12 |
| DOIs | |
| Publication status | Published - 2024 |
| MoE publication type | A1 Journal article-refereed |
Keywords
- human activity recognition (HAR)
- inertial measurement unit (IMU)
- multiply-and-accumulate multiply and accumulate (MAC)
- neural network accelerator
- smart sensor interface
- time-domain signal processing
- in-sensor processing
- Edge computing
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Dive into the research topics of 'A 22-nm All-Digital Time-Domain Neural Network Accelerator for Precision In-Sensor Processing'. Together they form a unique fingerprint.Projects
- 1 Finished
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WHISTLE: When integrated systems gain life experience: towards self-learning circuits with resource-efficient embedded artificial intelligence
Andraud, M. (Principal investigator), Adam, K. (Project Member), Zhong, X. (Project Member), Yao, L. (Project Member), Leslin, J. (Project Member), Bhowmick, S. (Project Member), Periasamy, K. (Project Member) & Ryynänen, J. (Principal investigator)
01/09/2020 → 31/08/2024
Project: RCF Academy Project
Equipment
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Aalto Electronics-ICT
Ryynänen, J. (Manager)
Department of Electronics and NanoengineeringFacility/equipment: Facility