A 150Mbit/s CMOS clock recovery PLL including a new improved phase detector and a fully integrated FLL

J. Routama, K. Koli, K. Halonen

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

    1 Citation (Scopus)
    Original languageEnglish
    Title of host publication1998 IEEE International Symposium on Circuits and Systems, 31.May-3.june 1998, Monterey, California, USA
    Pages159-162
    Publication statusPublished - 1998
    MoE publication typeA4 Article in a conference publication

    Keywords

    • Clock recovery PLL FLL

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