A 100–750 MS/s 11-Bit Time-to-Digital Converter With Cyclic-Coupled Ring Oscillator

Okko Jarvinen*, Vishnu Unnikrishnan, Waqas Siddiqui, Teuvo Korhonen, Kimmo Koli, Kari Stadius, Marko Kosunen, Jussi Ryynanen

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

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Abstract

This paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution. The architecture employs real-time quantization to reduce conversion time and hence maximize bandwidth. Furthermore, the CCRO phase progression is encoded with a bubble error suppression logic, thereby building resilience to delay mismatches from circuit/layout imperfections. The prototype circuit implemented in a 28 nm CMOS process demonstrates a combination of high resolution and high sample rate over wide range of sample rates. The TDC achieves its peak figure-of-merit (FoM) of 0.051 pJ/conv.-step at 100 MS/s while delivering 8.38-bit linear resolution and 15.4 ps time resolution, operating from a 0.55 V supply. The TDC demonstrates the highest reported linear resolution of 9.29 bits among converters operating above 100 MS/s, at 125 MS/s and 0.9 V supply, while achieving 4.4 ps time resolution and 0.16 pJ/conv.-step FoM. Further, the real-time quantizing architecture allows fast operation up to 750 MS/s, where the TDC delivers 6-bit linear resolution and 0.48 pJ/conv.-step FoM operating from 0.9 V supply.
Original languageEnglish
Pages (from-to)48147-48156
Number of pages10
JournalIEEE Access
Volume9
DOIs
Publication statusPublished - 24 Mar 2021
MoE publication typeA1 Journal article-refereed

Keywords

  • cyclic-coupled ring oscillator (CCRO)
  • time-to-digital converter (TDC)
  • sub-gate-delay
  • time resolution
  • bubble error
  • real-time
  • data converter

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