Agile Application Specific Risc-V Cores for Communications Signal Processing Acceleration

Project Details

Description

The emerging microelectronic trends of extremely complex accelerator SoC’s, AI-accelerators, and machine learning for control and adaptation set a requirement of for the companies to improve their capabilities. Companies need to strengthen their strategic expertise on field of System-on-Chip Implementations and implement customizable microprocessors to control those complex systems. SoC design has recently been identified as a strategic R&D area supported by Business Finland Veturi-initiative “"NOKIA – Suomesta teollisuuden 5G-verkkojen edelläkävijä".

Currently, the most prominent candidate for system controller is the open instruction set Risc-V microprocessor. Regardless of its open nature, designing and customizing the Risc-V implementations require deep and wide in-house knowledge on microelectronics and programming, as the threshold to use open processors is technically high. The implementation framework of open-source cores combines multitude of skills from programming to configurable and parametrized, generator-based silicon implementations, thus manifesting a paradigm shift in methods of processor design. Alternative to the in-house competence is outsourcing, which gives the edge in competition to the competing companies who have developed the required in-house competence. Therefore, outsourcing is not seen any more as successful strategy in global competition. The project aims for physical Risc-V core implementation on silicon, thus enhancing SoC competence of participating companies in Finland.
Short titleA-Core
AcronymA-Core
StatusNot started
Effective start/end date01/09/202131/08/2024